Searched defs:Srlv (Results 1 – 8 of 8) sorted by relevance
| /art/compiler/optimizing/ |
| D | code_generator_mips.cc | 2337 __ Srlv(dst, lhs, rhs_reg); in HandleShift() local
2349 __ Srlv(dst, lhs, rhs_reg); in HandleShift() local
2449 __ Srlv(TMP, TMP, AT); in HandleShift() local
2461 __ Srlv(dst_low, lhs_low, rhs_reg); in HandleShift() local
2468 __ Srlv(dst_high, lhs_high, rhs_reg); in HandleShift() local
2472 __ Srlv(dst_low, lhs_low, rhs_reg); in HandleShift() local
2480 __ Srlv(TMP, lhs_low, rhs_reg); in HandleShift() local
2484 __ Srlv(TMP, lhs_high, rhs_reg); in HandleShift() local
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| D | intrinsics_mips.cc | 2446 __ Srlv(out_hi, AT, TMP); in GenHighestOneBit() local
2453 __ Srlv(out_lo, AT, TMP); in GenHighestOneBit() local
2470 __ Srlv(AT, AT, TMP); // Srlv shifts in the range of [0;31] bits (lower 5 bits of arg). in GenHighestOneBit() local
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| D | intrinsics_mips64.cc | 2265 __ Srlv(AT, AT, TMP); in GenHighestOneBit() local
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| D | code_generator_mips64.cc | 2053 __ Srlv(dst, lhs, rhs_reg); in HandleShift() local
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| /art/compiler/utils/mips/ |
| D | assembler_mips_test.cc | 374 TEST_F(AssemblerMIPSTest, Srlv) { in TEST_F() argument
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| D | assembler_mips.cc | 735 void MipsAssembler::Srlv(Register rd, Register rt, Register rs) { in Srlv() function in art::mips::MipsAssembler
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64_test.cc | 1495 TEST_F(AssemblerMIPS64Test, Srlv) { in TEST_F() argument
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| D | assembler_mips64.cc | 500 void Mips64Assembler::Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Srlv() function in art::mips64::Mips64Assembler
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