| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc | 75 ShiftType ror; member
5135 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
|
| D | test-assembler-cond-rd-operand-rn-ror-amount-a32.cc | 74 ShiftType ror; member
1345 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
|
| D | test-assembler-cond-rd-operand-rn-ror-amount-t32.cc | 74 ShiftType ror; member
1233 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
|
| D | test-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc | 75 ShiftType ror; member
5135 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
|
| D | test-simulator-cond-rd-operand-rn-ror-amount-t32.cc | 141 ShiftType ror; member
726 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
|
| D | test-simulator-cond-rd-operand-rn-ror-amount-a32.cc | 141 ShiftType ror; member
726 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
|
| D | test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc | 142 ShiftType ror; member
1133 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
|
| D | test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc | 142 ShiftType ror; member
1133 ShiftType ror = kTests[i].operands.ror; in TestHelper() local
|
| /external/libconstrainedcrypto/ |
| D | sha256.c | 36 #define ror(value, bits) (((value) >> (bits)) | ((value) << (32 - (bits)))) macro
|
| /external/vixl/src/aarch32/ |
| D | instructions-aarch32.cc | 640 static inline uint32_t ror(uint32_t x, int i) { in ror() function
|
| D | assembler-aarch32.h | 2807 void ror(Register rd, Register rm, const Operand& operand) { in ror() function
2810 void ror(Condition cond, Register rd, Register rm, const Operand& operand) { in ror() function
2813 void ror(EncodingSize size, in ror() function
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 31 ror, enumerator
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 32 ror, enumerator
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 205 static inline uint64_t ror(uint64_t elt, unsigned size) { in ror() function
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | intel_tiled_memcpy.c | 62 ror(uint32_t n, uint32_t d) in ror() function
|
| /external/v8/src/x87/ |
| D | assembler-x87.h | 740 void ror(Register dst, uint8_t imm8) { ror(Operand(dst), imm8); } in ror() function
|
| D | assembler-x87.cc | 973 void Assembler::ror(const Operand& dst, uint8_t imm8) { in ror() function in v8::internal::Assembler
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 856 void ror(const Register& rd, const Register& rs, unsigned shift) { in ror() function
|
| /external/v8/src/arm64/ |
| D | assembler-arm64.h | 1275 void ror(const Register& rd, const Register& rs, unsigned shift) { in ror() function
|
| /external/valgrind/coregrind/ |
| D | m_transtab.c | 1452 UInt ror = 7; in HASH_TT() local
|
| /external/v8/src/compiler/ia32/ |
| D | code-generator-ia32.cc | 1321 __ ror(i.OutputOperand(), i.InputInt5(1)); in AssembleArchInstruction() local
|
| /external/v8/src/ia32/ |
| D | assembler-ia32.h | 747 void ror(Register dst, uint8_t imm8) { ror(Operand(dst), imm8); } in ror() function
|
| D | assembler-ia32.cc | 1102 void Assembler::ror(const Operand& dst, uint8_t imm8) { in ror() function in v8::internal::Assembler
|
| /external/v8/src/compiler/x87/ |
| D | code-generator-x87.cc | 1067 __ ror(i.OutputOperand(), i.InputInt5(1)); in AssembleArchInstruction() local
|
| /external/v8/src/crankshaft/ia32/ |
| D | lithium-codegen-ia32.cc | 1410 __ ror(ToRegister(left), shift_count); in DoShiftI() local
|