| /art/compiler/utils/arm64/ |
| D | assembler_arm64.cc | 74 static inline dwarf::Reg DWARFReg(CPURegister reg) { in DWARFReg() function
92 cfi_.RelOffset(DWARFReg(dst0), offset); in SpillRegisters()
99 cfi_.RelOffset(DWARFReg(dst0), offset); in SpillRegisters()
100 cfi_.RelOffset(DWARFReg(dst1), offset + size); in SpillRegisters()
106 cfi_.RelOffset(DWARFReg(dst0), offset); in SpillRegisters()
118 cfi_.Restore(DWARFReg(dst0)); in UnspillRegisters()
125 cfi_.Restore(DWARFReg(dst0)); in UnspillRegisters()
126 cfi_.Restore(DWARFReg(dst1)); in UnspillRegisters()
132 cfi_.Restore(DWARFReg(dst0)); in UnspillRegisters()
|
| /art/compiler/utils/x86_64/ |
| D | jni_macro_assembler_x86_64.cc | 27 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg() function
30 static dwarf::Reg DWARFReg(FloatRegister reg) { in DWARFReg() function
52 cfi().RelOffset(DWARFReg(spill.AsCpuRegister().AsRegister()), 0); in BuildFrame()
69 cfi().RelOffset(DWARFReg(spill.AsXmmRegister().AsFloatRegister()), offset); in BuildFrame()
116 cfi().Restore(DWARFReg(spill.AsXmmRegister().AsFloatRegister())); in RemoveFrame()
129 cfi().Restore(DWARFReg(spill.AsCpuRegister().AsRegister())); in RemoveFrame()
|
| /art/compiler/optimizing/ |
| D | common_arm.h | 41 inline dwarf::Reg DWARFReg(vixl::aarch32::Register reg) { in DWARFReg() function
45 inline dwarf::Reg DWARFReg(vixl::aarch32::SRegister reg) { in DWARFReg() function
|
| D | code_generator_mips64.cc | 1140 static dwarf::Reg DWARFReg(GpuRegister reg) { in DWARFReg() function
1144 static dwarf::Reg DWARFReg(FpuRegister reg) { in DWARFReg() function
1180 __ cfi().RelOffset(DWARFReg(reg), ofs); in GenerateFrameEntry()
1189 __ cfi().RelOffset(DWARFReg(reg), ofs); in GenerateFrameEntry()
1219 __ cfi().Restore(DWARFReg(reg)); in GenerateFrameExit()
1228 __ cfi().Restore(DWARFReg(reg)); in GenerateFrameExit()
|
| D | code_generator_x86_64.cc | 1253 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg() function
1257 static dwarf::Reg DWARFReg(FloatRegister reg) { in DWARFReg() function
1283 __ cfi().RelOffset(DWARFReg(reg), 0); in GenerateFrameEntry()
1297 __ cfi().RelOffset(DWARFReg(kFpuCalleeSaves[i]), offset); in GenerateFrameEntry()
1324 __ cfi().Restore(DWARFReg(kFpuCalleeSaves[i])); in GenerateFrameExit()
1337 __ cfi().Restore(DWARFReg(reg)); in GenerateFrameExit()
|
| D | code_generator_arm_vixl.cc | 46 using helpers::DWARFReg;
2660 GetAssembler()->cfi().RelOffsetForMany(DWARFReg(kMethodRegister), in GenerateFrameEntry()
2672 GetAssembler()->cfi().RelOffsetForMany(DWARFReg(s0), 0, fpu_spill_mask_, kArmWordSize); in GenerateFrameEntry()
2713 GetAssembler()->cfi().RestoreMany(DWARFReg(vixl32::SRegister(0)), fpu_spill_mask_); in GenerateFrameExit()
|
| D | code_generator_x86.cc | 1058 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg() function
1083 __ cfi().RelOffset(DWARFReg(reg), 0); in GenerateFrameEntry()
1115 __ cfi().Restore(DWARFReg(reg)); in GenerateFrameExit()
|
| D | code_generator_mips.cc | 1333 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg() function
1376 __ cfi().RelOffset(DWARFReg(reg), ofs); in GenerateFrameEntry()
1416 __ cfi().Restore(DWARFReg(reg)); in GenerateFrameExit()
|
| /art/compiler/utils/arm/ |
| D | jni_macro_assembler_arm_vixl.cc | 47 static dwarf::Reg DWARFReg(vixl32::Register reg) { in DWARFReg() function
51 static dwarf::Reg DWARFReg(vixl32::SRegister reg) { in DWARFReg() function
76 cfi().RelOffsetForMany(DWARFReg(r0), 0, core_spill_mask, kFramePointerSize); in BuildFrame()
85 cfi().RelOffsetForMany(DWARFReg(s0), 0, fp_spill_mask, kFramePointerSize); in BuildFrame()
147 cfi().RestoreMany(DWARFReg(s0), fp_spill_mask); in RemoveFrame()
|
| /art/compiler/utils/x86/ |
| D | jni_macro_assembler_x86.cc | 36 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg() function
57 cfi().RelOffset(DWARFReg(spill), 0); in BuildFrame()
99 cfi().Restore(DWARFReg(spill)); in RemoveFrame()
|
| /art/compiler/utils/mips64/ |
| D | assembler_mips64.cc | 3079 static dwarf::Reg DWARFReg(GpuRegister reg) { in DWARFReg() function
3098 cfi_.RelOffset(DWARFReg(RA), stack_offset); in BuildFrame()
3103 cfi_.RelOffset(DWARFReg(reg), stack_offset); in BuildFrame()
3141 cfi_.Restore(DWARFReg(reg)); in RemoveFrame()
3145 cfi_.Restore(DWARFReg(RA)); in RemoveFrame()
|
| /art/compiler/utils/mips/ |
| D | assembler_mips.cc | 4616 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg() function
4635 cfi_.RelOffset(DWARFReg(RA), stack_offset); in BuildFrame()
4640 cfi_.RelOffset(DWARFReg(reg), stack_offset); in BuildFrame()
4677 cfi_.Restore(DWARFReg(reg)); in RemoveFrame()
4681 cfi_.Restore(DWARFReg(RA)); in RemoveFrame()
|