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Searched refs:S1 (Results 1 – 22 of 22) sorted by relevance

/art/runtime/arch/mips/
Dregisters_mips.h47 S1 = 17, enumerator
62 TR = S1, // ART Thread Register
Dquick_method_frame_info_mips.h39 (1 << art::mips::S0) | (1 << art::mips::S1);
45 (1 << art::mips::S0) | (1 << art::mips::S1) | (1 << art::mips::T8) | (1 << art::mips::T9);
/art/runtime/arch/mips64/
Dregisters_mips64.h47 S1 = 17, enumerator
62 TR = S1, // ART Thread Register
Dquick_method_frame_info_mips64.h41 (1 << art::mips64::S0) | (1 << art::mips64::S1);
48 (1 << art::mips64::S0) | (1 << art::mips64::S1) | (1 << art::mips64::T8) |
/art/compiler/utils/arm/
Dmanaged_register_arm_test.cc78 reg = ArmManagedRegister::FromSRegister(S1); in TEST()
85 EXPECT_EQ(S1, reg.AsSRegister()); in TEST()
135 EXPECT_EQ(S1, reg.AsOverlappingDRegisterHigh()); in TEST()
312 EXPECT_TRUE(!reg_R1.Equals(ArmManagedRegister::FromSRegister(S1))); in TEST()
322 EXPECT_TRUE(!reg_R8.Equals(ArmManagedRegister::FromSRegister(S1))); in TEST()
331 EXPECT_TRUE(!reg_S0.Equals(ArmManagedRegister::FromSRegister(S1))); in TEST()
336 ArmManagedRegister reg_S1 = ArmManagedRegister::FromSRegister(S1); in TEST()
341 EXPECT_TRUE(reg_S1.Equals(ArmManagedRegister::FromSRegister(S1))); in TEST()
465 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S1))); in TEST()
487 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S1))); in TEST()
[all …]
/art/compiler/utils/arm64/
Dmanaged_register_arm64_test.cc181 sreg = Arm64ManagedRegister::FromSRegister(S1); in TEST()
189 EXPECT_EQ(S1, reg.AsOverlappingSRegister()); in TEST()
294 EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
310 EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
320 EXPECT_TRUE(!reg_W12.Equals(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
328 EXPECT_TRUE(!reg_S0.Equals(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
332 Arm64ManagedRegister reg_S1 = Arm64ManagedRegister::FromSRegister(S1); in TEST()
338 EXPECT_TRUE(reg_S1.Equals(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
387 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
409 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
[all …]
/art/runtime/arch/arm/
Dregisters_arm.h59 S1 = 1, enumerator
Dcontext_arm.cc83 fprs_[S1] = nullptr; in SmashCallerSaves()
Dquick_method_frame_info_arm.h46 (1 << art::arm::S0) | (1 << art::arm::S1) | (1 << art::arm::S2) | (1 << art::arm::S3) |
/art/runtime/arch/arm64/
Dregisters_arm64.h155 S1 = 1, enumerator
/art/compiler/trampolines/
Dtrampoline_compiler.cc152 __ LoadFromOffset(kLoadWord, T9, S1, offset.Int32Value()); in CreateTrampoline()
184 __ LoadFromOffset(kLoadDoubleword, T9, S1, offset.Int32Value()); in CreateTrampoline()
/art/compiler/jni/quick/arm64/
Dcalling_convention_arm64.cc47 S0, S1, S2, S3, S4, S5, S6, S7
/art/compiler/jni/quick/arm/
Dcalling_convention_arm.cc50 S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
/art/compiler/utils/mips64/
Dmanaged_register_mips64_test.cc231 EXPECT_FALSE(reg_S2.Equals(Mips64ManagedRegister::FromGpuRegister(S1))); in TEST()
260 EXPECT_FALSE(reg_W0.Equals(Mips64ManagedRegister::FromGpuRegister(S1))); in TEST()
270 EXPECT_FALSE(reg_W31.Equals(Mips64ManagedRegister::FromGpuRegister(S1))); in TEST()
Dassembler_mips64.cc3224 StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), S1, thr_offs.Int32Value()); in StoreStackOffsetToThread()
3228 StoreToOffset(kStoreDoubleword, SP, S1, thr_offs.Int32Value()); in StoreStackPointerToThread()
3245 return EmitLoad(mdest, S1, src.Int32Value(), size); in LoadFromThread()
3276 LoadFromOffset(kLoadDoubleword, dest.AsGpuRegister(), S1, offs.Int32Value()); in LoadRawPtrFromThread()
3322 LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), S1, thr_offs.Int32Value()); in CopyRawPtrFromThread()
3334 S1, thr_offs.Int32Value()); in CopyRawPtrToThread()
3536 Move(tr.AsMips64().AsGpuRegister(), S1); in GetCurrentThread()
3541 StoreToOffset(kStoreDoubleword, S1, SP, offset.Int32Value()); in GetCurrentThread()
3549 S1, in ExceptionPoll()
3566 S1, in EmitExceptionPoll()
Dassembler_mips64_test.cc107 registers_.push_back(new mips64::GpuRegister(mips64::S1)); in SetUpHelpers()
140 secondary_register_names_.emplace(mips64::GpuRegister(mips64::S1), "s1"); in SetUpHelpers()
/art/compiler/utils/mips/
Dassembler_mips32r5_test.cc96 registers_.push_back(new mips::Register(mips::S1)); in SetUpHelpers()
129 secondary_register_names_.emplace(mips::Register(mips::S1), "s1"); in SetUpHelpers()
Dassembler_mips.cc4775 S1, thr_offs.Int32Value()); in StoreStackOffsetToThread()
4779 StoreToOffset(kStoreWord, SP, S1, thr_offs.Int32Value()); in StoreStackPointerToThread()
4796 return EmitLoad(mdest, S1, src.Int32Value(), size); in LoadFromThread()
4826 LoadFromOffset(kLoadWord, dest.AsCoreRegister(), S1, offs.Int32Value()); in LoadRawPtrFromThread()
4883 S1, thr_offs.Int32Value()); in CopyRawPtrFromThread()
4896 S1, thr_offs.Int32Value()); in CopyRawPtrToThread()
5068 Move(tr.AsMips().AsCoreRegister(), S1); in GetCurrentThread()
5073 StoreToOffset(kStoreWord, S1, SP, offset.Int32Value()); in GetCurrentThread()
5080 S1, Thread::ExceptionOffset<kMipsPointerSize>().Int32Value()); in ExceptionPoll()
5094 LoadFromOffset(kLoadWord, T9, S1, in EmitExceptionPoll()
Dassembler_mips32r6_test.cc109 registers_.push_back(new mips::Register(mips::S1)); in SetUpHelpers()
142 secondary_register_names_.emplace(mips::Register(mips::S1), "s1"); in SetUpHelpers()
Dassembler_mips_test.cc74 registers_.push_back(new mips::Register(mips::S1)); in SetUpHelpers()
107 secondary_register_names_.emplace(mips::Register(mips::S1), "s1"); in SetUpHelpers()
/art/compiler/optimizing/
Dcode_generator_mips64.h55 { S0, S1, S2, S3, S4, S5, S6, S7, GP, S8, RA };
Dcode_generator_mips.h57 { S0, S1, S2, S3, S4, S5, S6, S7, FP, RA };