| /art/compiler/optimizing/ |
| D | intrinsics_mips.cc | 266 __ Sll(TMP, in, 24); in GenReverse() local
268 __ Sll(out, in, 16); in GenReverse() local
282 __ Sll(TMP, in, 16); in GenReverse() local
288 __ Sll(TMP, TMP, 8); in GenReverse() local
299 __ Sll(TMP, TMP, 4); in GenReverse() local
305 __ Sll(TMP, TMP, 2); in GenReverse() local
311 __ Sll(TMP, TMP, 1); in GenReverse() local
334 __ Sll(TMP, in_lo, 16); in GenReverse() local
339 __ Sll(AT, in_hi, 16); in GenReverse() local
347 __ Sll(out_hi, out_hi, 8); in GenReverse() local
[all …]
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| D | code_generator_mips.cc | 940 __ Sll(index_reg, index_reg, TIMES_4); in EmitNativeCode() local
2317 __ Sll(dst, lhs, shift_value); in HandleShift() local
2326 __ Sll(TMP, lhs, (kMipsBitsPerWord - shift_value) & shift_mask); in HandleShift() local
2370 __ Sll(dst_low, lhs_low, shift_value); in HandleShift() local
2387 __ Sll(dst_low, lhs_low, shift_value); in HandleShift() local
2389 __ Sll(dst_high, lhs_high, shift_value); in HandleShift() local
2393 __ Sll(TMP, lhs_high, kMipsBitsPerWord - shift_value); in HandleShift() local
2398 __ Sll(TMP, lhs_high, kMipsBitsPerWord - shift_value); in HandleShift() local
2403 __ Sll(dst_low, lhs_high, kMipsBitsPerWord - shift_value); in HandleShift() local
2406 __ Sll(dst_high, lhs_low, kMipsBitsPerWord - shift_value); in HandleShift() local
[all …]
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| D | code_generator_mips64.cc | 880 __ Sll(index_reg, index_reg, TIMES_4); in EmitNativeCode() local
2014 __ Sll(dst, lhs, shift_value); in HandleShift() local
3175 __ Sll(out, out, 32 - ctz_imm); in DivRemByPowerOfTwo() local
4598 __ Sll(temp_reg, temp_reg, 31 - LockWord::kReadBarrierStateShift); in GenerateReferenceLoadWithBakerReadBarrier() local
6025 __ Sll(dst, src, 0); in VisitTypeConversion() local
6036 __ Sll(dst, src, 0); in VisitTypeConversion() local
6048 __ Sll(dst, src, 0); in VisitTypeConversion() local
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| /art/compiler/utils/mips/ |
| D | assembler_mips_test.cc | 358 TEST_F(AssemblerMIPSTest, Sll) { in TEST_F() argument
359 DriverStr(RepeatRRIb(&mips::MipsAssembler::Sll, 5, "sll ${reg1}, ${reg2}, {imm}"), "Sll"); in TEST_F()
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| D | assembler_mips.h | 260 void Sll(Register rd, Register rt, int shamt);
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| D | assembler_mips.cc | 711 void MipsAssembler::Sll(Register rd, Register rt, int shamt) { in Sll() function in art::mips::MipsAssembler
781 Sll(tmp, src_idx, shamt); in ShiftAndAdd()
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64_test.cc | 1475 TEST_F(AssemblerMIPS64Test, Sll) { in TEST_F() argument
1476 DriverStr(RepeatRRIb(&mips64::Mips64Assembler::Sll, 5, "sll ${reg1}, ${reg2}, {imm}"), "sll"); in TEST_F()
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| D | assembler_mips64.h | 489 void Sll(GpuRegister rd, GpuRegister rt, int shamt);
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| D | assembler_mips64.cc | 476 void Mips64Assembler::Sll(GpuRegister rd, GpuRegister rt, int shamt) { in Sll() function in art::mips64::Mips64Assembler
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