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Searched refs:ADDR32 (Results 1 – 8 of 8) sorted by relevance

/external/syslinux/gpxe/src/arch/i386/prefix/
Dunnrv2b.S71 #define ADDR32 addr32 macro
93 #define ADDR32 macro
119 ADDR32 movsb
137 ADDR32 movb (%xSI), %al /* m_off = (m_off - 3)*256 + src[ilen++] */
161 ADDR32 lea (%xBP,%xDI), %xSI /* m_pos = dst + olen + -m_off */
163 es ADDR32 movsb /* dst[olen++] = *m_pos++ while(m_len > 0) */
172 ADDR32 movl (%xSI), %ebx
/external/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.td117 defm ADDR32 : SystemZRegClass<"ADDR32", [i32], 32, (sub GR32Bit, R0L)>;
120 // Not used directly, but needs to exist for ADDR32 and ADDR64 subregs
DSystemZInstrInfo.td1536 ADDR32:$bitshift, ADDR32:$negbitshift,
1540 ADDR32:$bitshift, ADDR32:$negbitshift,
DSystemZInstrFormats.td2529 (ins bdaddr20only:$ptr, operand:$src2, ADDR32:$bitshift,
2530 ADDR32:$negbitshift, uimm32:$bitsize),
2531 [(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift,
2532 ADDR32:$negbitshift, uimm32:$bitsize))]> {
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZRegisterInfo.td171 def ADDR32 : RegisterClass<"SystemZ", [i32], 32, (sub GR32, R0W)>;
179 let SubRegClasses = [(ADDR32 subreg_32bit)];
/external/elfutils/backends/
Dppc_reloc.def32 RELOC_TYPE (ADDR32, REL|EXEC|DYN)
Dppc64_reloc.def32 RELOC_TYPE (ADDR32, REL|EXEC|DYN)
/external/valgrind/
Dconfigure.ac2473 # does the x86/amd64 assembler understand ADDR32 ?