| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | Thumb1RegisterInfo.cpp | 92 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmInReg() argument
99 (BaseReg != 0 && !isARMLowRegister(BaseReg)); in emitThumbRegPlusImmInReg()
111 assert(BaseReg == ARM::SP && "Unexpected!"); in emitThumbRegPlusImmInReg()
134 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); in emitThumbRegPlusImmInReg()
136 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmInReg()
169 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmediate() argument
185 if (DestReg == BaseReg && BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
191 } else if (!isSub && BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
207 if (DestReg != BaseReg) in emitThumbRegPlusImmediate()
229 DestReg, BaseReg, NumBytes, true, in emitThumbRegPlusImmediate()
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| D | Thumb2InstrInfo.cpp | 176 unsigned DestReg, unsigned BaseReg, int NumBytes, in emitT2RegPlusImmediate() argument
184 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate()
206 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate()
213 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate()
224 if (DestReg == ARM::SP && BaseReg != ARM::SP) { in emitT2RegPlusImmediate()
227 .addReg(BaseReg).setMIFlags(MIFlags)); in emitT2RegPlusImmediate()
228 BaseReg = ARM::SP; in emitT2RegPlusImmediate()
233 if (BaseReg == ARM::SP) { in emitT2RegPlusImmediate()
239 .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags)); in emitT2RegPlusImmediate()
257 assert(DestReg != ARM::SP && BaseReg != ARM::SP); in emitT2RegPlusImmediate()
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| /external/swiftshader/third_party/LLVM/lib/Transforms/Utils/ |
| D | AddrModeMatcher.cpp | 42 if (BaseReg) { in print()
45 WriteAsOperand(OS, BaseReg, /*PrintType=*/false); in print()
275 AddrMode.BaseReg = AddrInst->getOperand(0); in MatchOperationAddr()
288 AddrMode.BaseReg = AddrInst->getOperand(0); in MatchOperationAddr()
356 AddrMode.BaseReg = Addr; in MatchAddr()
361 AddrMode.BaseReg = 0; in MatchAddr()
523 Value *BaseReg = AMAfter.BaseReg, *ScaledReg = AMAfter.ScaledReg; in IsProfitableToFoldIntoAddressingMode() local
527 if (ValueAlreadyLiveAtInst(BaseReg, AMBefore.BaseReg, AMBefore.ScaledReg)) in IsProfitableToFoldIntoAddressingMode()
528 BaseReg = 0; in IsProfitableToFoldIntoAddressingMode()
529 if (ValueAlreadyLiveAtInst(ScaledReg, AMBefore.BaseReg, AMBefore.ScaledReg)) in IsProfitableToFoldIntoAddressingMode()
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| /external/llvm/lib/Target/ARM/ |
| D | ThumbRegisterInfo.cpp | 125 const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, in emitThumbRegPlusImmInReg() argument
130 (BaseReg != 0 && !isARMLowRegister(BaseReg)); in emitThumbRegPlusImmInReg()
142 assert(BaseReg == ARM::SP && "Unexpected!"); in emitThumbRegPlusImmInReg()
168 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); in emitThumbRegPlusImmInReg()
170 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmInReg()
181 unsigned BaseReg, int NumBytes, in emitThumbRegPlusImmediate() argument
212 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
224 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
230 } else if (DestReg == BaseReg) { in emitThumbRegPlusImmediate()
233 } else if (isARMLowRegister(BaseReg)) { in emitThumbRegPlusImmediate()
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| D | Thumb2InstrInfo.cpp | 224 unsigned BaseReg, int NumBytes, in emitT2RegPlusImmediate() argument
228 if (NumBytes == 0 && DestReg != BaseReg) { in emitT2RegPlusImmediate()
230 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate()
240 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate()
262 .addReg(BaseReg) in emitT2RegPlusImmediate()
273 .addReg(BaseReg) in emitT2RegPlusImmediate()
285 if (DestReg == ARM::SP && BaseReg != ARM::SP) { in emitT2RegPlusImmediate()
288 .addReg(BaseReg).setMIFlags(MIFlags)); in emitT2RegPlusImmediate()
289 BaseReg = ARM::SP; in emitT2RegPlusImmediate()
294 if (BaseReg == ARM::SP) { in emitT2RegPlusImmediate()
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| D | ARMBaseRegisterInfo.h | 151 unsigned BaseReg, int FrameIdx,
153 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
155 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
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| /external/llvm/lib/CodeGen/ |
| D | LocalStackSlotAllocation.cpp | 255 lookupCandidateBaseReg(unsigned BaseReg, in lookupCandidateBaseReg() argument
264 return TRI->isFrameOffsetLegal(&MI, BaseReg, Offset); in lookupCandidateBaseReg()
326 unsigned BaseReg = 0; in insertFrameReferenceRegisters() local
362 lookupCandidateBaseReg(BaseReg, BaseOffset, FrameSizeAdjust, in insertFrameReferenceRegisters()
364 DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n"); in insertFrameReferenceRegisters()
381 BaseReg, BaseOffset, FrameSizeAdjust, in insertFrameReferenceRegisters()
390 BaseReg = Fn.getRegInfo().createVirtualRegister(RC); in insertFrameReferenceRegisters()
392 DEBUG(dbgs() << " Materializing base register " << BaseReg << in insertFrameReferenceRegisters()
398 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx, in insertFrameReferenceRegisters()
409 assert(BaseReg != 0 && "Unable to allocate virtual base register!"); in insertFrameReferenceRegisters()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | LocalStackSlotAllocation.cpp | 294 unsigned BaseReg = 0; in insertFrameReferenceRegisters() local
314 BaseReg = RegOffset.first; in insertFrameReferenceRegisters()
322 BaseReg = Fn.getRegInfo().createVirtualRegister(RC); in insertFrameReferenceRegisters()
324 DEBUG(dbgs() << " Materializing base register " << BaseReg << in insertFrameReferenceRegisters()
331 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx, in insertFrameReferenceRegisters()
342 std::pair<unsigned, int64_t>(BaseReg, BaseOffset)); in insertFrameReferenceRegisters()
346 assert(BaseReg != 0 && "Unable to allocate virtual base register!"); in insertFrameReferenceRegisters()
350 TRI->resolveFrameIndex(I, BaseReg, Offset); in insertFrameReferenceRegisters()
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| /external/swiftshader/third_party/LLVM/include/llvm/Transforms/Utils/ |
| D | AddrModeMatcher.h | 37 Value *BaseReg; member
39 ExtAddrMode() : BaseReg(0), ScaledReg(0) {} in ExtAddrMode()
44 return (BaseReg == O.BaseReg) && (ScaledReg == O.ScaledReg) &&
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 264 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anondb7da0ad0111::X86AsmParser::IntelExprStateMachine
274 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0), in IntelExprStateMachine()
278 unsigned getBaseReg() { return BaseReg; } in getBaseReg()
384 if (!BaseReg) { in onPlus()
385 BaseReg = TmpReg; in onPlus()
421 if (!BaseReg) { in onMinus()
422 BaseReg = TmpReg; in onMinus()
600 if (!BaseReg) { in onRBrac()
601 BaseReg = TmpReg; in onRBrac()
716 CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg,
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| D | X86Operand.h | 55 unsigned BaseReg; member
117 return Mem.BaseReg; in getMemBaseReg()
503 Res->Mem.BaseReg = 0;
517 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
522 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
530 Res->Mem.BaseReg = BaseReg;
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64StorePairSuppress.cpp | 146 unsigned BaseReg; in runOnMachineFunction() local
148 if (TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI)) { in runOnMachineFunction()
149 if (PrevBaseReg == BaseReg) { in runOnMachineFunction()
158 PrevBaseReg = BaseReg; in runOnMachineFunction()
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| D | AArch64RegisterInfo.h | 77 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
79 void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg,
82 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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| D | AArch64RegisterInfo.cpp | 314 unsigned BaseReg, in isFrameOffsetLegal() argument
325 unsigned BaseReg, in materializeFrameBaseRegister() argument
337 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
340 BuildMI(*MBB, Ins, DL, MCID, BaseReg) in materializeFrameBaseRegister()
346 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex() argument
358 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII); in resolveFrameIndex()
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| D | AArch64LoadStoreOptimizer.cpp | 147 unsigned BaseReg, int Offset);
1104 unsigned BaseReg = getLdStBaseOp(LoadMI).getReg(); in findMatchingStore() local
1130 BaseReg == getLdStBaseOp(MI).getReg() && in findMatchingStore()
1145 if (ModifiedRegs[BaseReg]) in findMatchingStore()
1217 unsigned BaseReg = getLdStBaseOp(FirstMI).getReg(); in findMatchingInsn() local
1269 if (BaseReg == MIBaseReg && ((Offset == MIOffset + OffsetStride) || in findMatchingInsn()
1347 if (ModifiedRegs[BaseReg]) in findMatchingInsn()
1422 unsigned BaseReg, int Offset) { in isMatchingUpdateInsn() argument
1441 if (MI.getOperand(0).getReg() != BaseReg || in isMatchingUpdateInsn()
1442 MI.getOperand(1).getReg() != BaseReg) in isMatchingUpdateInsn()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/InstPrinter/ |
| D | X86ATTInstPrinter.cpp | 110 const MCOperand &BaseReg = MI->getOperand(Op); in printMemReference() local
123 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) in printMemReference()
130 if (IndexReg.getReg() || BaseReg.getReg()) { in printMemReference()
132 if (BaseReg.getReg()) in printMemReference()
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| D | X86IntelInstPrinter.cpp | 97 const MCOperand &BaseReg = MI->getOperand(Op); in printMemReference() local
112 if (BaseReg.getReg()) { in printMemReference()
132 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printMemReference()
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| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinRegisterInfo.cpp | 207 unsigned BaseReg = BF::FP; in eliminateFrameIndex() local
211 BaseReg = BF::SP; in eliminateFrameIndex()
223 MI.getOperand(FIPos).ChangeToRegister(BaseReg, false); in eliminateFrameIndex()
231 if (BaseReg == BF::FP && isUInt<7>(-Offset)) { in eliminateFrameIndex()
258 MI.getOperand(2).ChangeToRegister(BaseReg, false); in eliminateFrameIndex()
272 .addReg(BaseReg); in eliminateFrameIndex()
296 MI.getOperand(FIPos).ChangeToRegister(BaseReg, false); in eliminateFrameIndex()
308 MI.getOperand(FIPos).ChangeToRegister(BaseReg, false); in eliminateFrameIndex()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 135 unsigned BaseReg; member
181 return Mem.BaseReg; in getMemBaseReg()
344 Res->Mem.BaseReg = 0; in CreateMem()
352 unsigned BaseReg, unsigned IndexReg, in CreateMem()
356 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!"); in CreateMem()
364 Res->Mem.BaseReg = BaseReg; in CreateMem()
380 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0); in isSrcOp()
389 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0; in isDstOp()
581 unsigned BaseReg = 0, IndexReg = 0, Scale = 1; in ParseMemOperand() local
585 if (ParseRegister(BaseReg, L, L)) return 0; in ParseMemOperand()
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is16BitMemOperand() local
64 if (is16BitMode(STI) && BaseReg.getReg() == 0 && in Is16BitMemOperand()
67 if ((BaseReg.getReg() != 0 && in Is16BitMemOperand()
68 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || in Is16BitMemOperand()
206 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is32BitMemOperand() local
209 if ((BaseReg.getReg() != 0 && in Is32BitMemOperand()
210 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || in Is32BitMemOperand()
214 if (BaseReg.getReg() == X86::EIP) { in Is32BitMemOperand()
225 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is64BitMemOperand() local
228 if ((BaseReg.getReg() != 0 && in Is64BitMemOperand()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.h | 68 unsigned BaseReg, int FrameIdx,
71 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
74 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
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| /external/llvm/lib/Target/Lanai/AsmParser/ |
| D | LanaiAsmParser.cpp | 114 unsigned BaseReg; member
156 return Mem.BaseReg; in getMemBaseReg()
598 Op->Mem.BaseReg = 0; in MorphToMemImm()
606 MorphToMemRegReg(unsigned BaseReg, std::unique_ptr<LanaiOperand> Op, in MorphToMemRegReg()
610 Op->Mem.BaseReg = BaseReg; in MorphToMemRegReg()
618 MorphToMemRegImm(unsigned BaseReg, std::unique_ptr<LanaiOperand> Op, in MorphToMemRegImm()
622 Op->Mem.BaseReg = BaseReg; in MorphToMemRegImm()
862 unsigned BaseReg = 0; in parseMemoryOperand() local
919 BaseReg = Op->getReg(); in parseMemoryOperand()
947 if (!BaseReg || Lexer.isNot(AsmToken::RBrac)) { in parseMemoryOperand()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 231 unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset, in emitStoreWithImmOffset() argument
235 emitRRI(Opcode, SrcReg, BaseReg, Offset, IDLoc, STI); in emitStoreWithImmOffset()
257 if (BaseReg != Mips::ZERO) in emitStoreWithImmOffset()
258 emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI); in emitStoreWithImmOffset()
266 unsigned Opcode, unsigned SrcReg, unsigned BaseReg, MCOperand &HiOperand, in emitStoreWithSymOffset() argument
274 if (BaseReg != Mips::ZERO) in emitStoreWithSymOffset()
275 emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI); in emitStoreWithSymOffset()
285 unsigned BaseReg, int64_t Offset, in emitLoadWithImmOffset() argument
289 emitRRI(Opcode, DstReg, BaseReg, Offset, IDLoc, STI); in emitLoadWithImmOffset()
310 if (BaseReg != Mips::ZERO) in emitLoadWithImmOffset()
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| /external/llvm/lib/Target/X86/InstPrinter/ |
| D | X86ATTInstPrinter.cpp | 197 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); in printMemReference() local
212 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) in printMemReference()
219 if (IndexReg.getReg() || BaseReg.getReg()) { in printMemReference()
221 if (BaseReg.getReg()) in printMemReference()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.h | 128 unsigned BaseReg, int FrameIdx,
130 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
132 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
|