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Searched refs:BuildMI (Results 1 – 25 of 277) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCFrameLowering.cpp136 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
140 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
145 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
149 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
154 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
158 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
162 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
313 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0); in emitPrologue()
316 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) in emitPrologue()
322 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) in emitPrologue()
[all …]
DPPCInstrInfo.cpp141 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) in commuteInstruction()
165 BuildMI(MBB, MI, DL, get(PPC::NOP)); in insertNoop()
288 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); in InsertBranch()
290 BuildMI(&MBB, DL, get(PPC::BCC)) in InsertBranch()
296 BuildMI(&MBB, DL, get(PPC::BCC)) in InsertBranch()
298 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB); in InsertBranch()
324 BuildMI(MBB, I, DL, MCID, DestReg) in copyPhysReg()
327 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
339 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) in StoreRegToStackSlot()
347 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11)); in StoreRegToStackSlot()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUFrameLowering.cpp119 BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)).addSym(FrameLabel); in emitPrologue()
124 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16) in emitPrologue()
128 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize) in emitPrologue()
131 BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1) in emitPrologue()
136 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2) in emitPrologue()
139 BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2) in emitPrologue()
141 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQXr32), SPU::R1) in emitPrologue()
144 BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1) in emitPrologue()
147 BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2) in emitPrologue()
150 BuildMI(MBB, MBBI, dl, TII.get(SPU::LQXr128), SPU::R2) in emitPrologue()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinInstrInfo.cpp92 BuildMI(&MBB, DL, get(BF::JUMPa)).addMBB(TBB); in InsertBranch()
105 BuildMI(MBB, I, DL, get(BF::MOVE), DestReg) in copyPhysReg()
111 BuildMI(MBB, I, DL, get(BF::SLL16i), DestReg) in copyPhysReg()
119 BuildMI(MBB, I, DL, get(BF::MOVENCC_z), DestReg) in copyPhysReg()
121 BuildMI(MBB, I, DL, get(BF::BITTGL), DestReg).addReg(DestReg).addImm(0); in copyPhysReg()
125 BuildMI(MBB, I, DL, get(BF::MOVECC_zext), DestReg) in copyPhysReg()
133 BuildMI(MBB, I, DL, get(BF::SETEQri_not), DestReg) in copyPhysReg()
138 BuildMI(MBB, I, DL, get(BF::MOVECC_nz), DestReg) in copyPhysReg()
146 BuildMI(MBB, I, DL, get(BF::MOVE_ncccc), DestReg) in copyPhysReg()
152 BuildMI(MBB, I, DL, get(BF::MOVE_ccncc), DestReg) in copyPhysReg()
[all …]
DBlackfinRegisterInfo.cpp97 BuildMI(MBB, I, DL, TII.get(BF::ADDpp_imm7), Reg) in adjustRegister()
108 BuildMI(MBB, I, DL, TII.get(BF::ADDpp), Reg) in adjustRegister()
115 BuildMI(MBB, I, DL, TII.get(BF::ADD), Reg) in adjustRegister()
128 BuildMI(MBB, I, DL, TII.get(BF::LOADimm7), Reg).addImm(value); in loadConstant()
133 BuildMI(MBB, I, DL, TII.get(BF::LOADuimm16), Reg).addImm(value); in loadConstant()
138 BuildMI(MBB, I, DL, TII.get(BF::LOADimm16), Reg).addImm(value); in loadConstant()
143 BuildMI(MBB, I, DL, in loadConstant()
147 BuildMI(MBB, I, DL, in loadConstant()
270 BuildMI(MBB, II, DL, TII.get(BF::ADDpp), ScratchReg) in eliminateFrameIndex()
285 BuildMI(MBB, II, DL, TII.get(BF::MOVENCC_z), ScratchReg) in eliminateFrameIndex()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsFrameLowering.cpp128 BuildMI(MBB, I, DL, TII->get(Mips::NOAT)); in expandRegLargeImmPair()
129 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::AT).addImm(ImmHi); in expandRegLargeImmPair()
130 BuildMI(MBB, I, DL, TII->get(Mips::ADDu), Mips::AT).addReg(OrigReg) in expandRegLargeImmPair()
165 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER)); in emitPrologue()
169 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD)) in emitPrologue()
171 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO)); in emitPrologue()
183 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP) in emitPrologue()
188 BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO)); in emitPrologue()
192 BuildMI(MBB, MBBI, dl, in emitPrologue()
209 BuildMI(MBB, MBBI, dl, in emitPrologue()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaFrameLowering.cpp56 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAHg), Alpha::R29) in emitPrologue()
58 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAg), Alpha::R29) in emitPrologue()
61 BuildMI(MBB, MBBI, dl, TII.get(Alpha::ALTENT)) in emitPrologue()
82 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) in emitPrologue()
85 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30) in emitPrologue()
87 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30) in emitPrologue()
95 BuildMI(MBB, MBBI, dl, TII.get(Alpha::STQ)) in emitPrologue()
98 BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R15) in emitPrologue()
123 BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15) in emitEpilogue()
126 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDQ), Alpha::R15) in emitEpilogue()
[all …]
DAlphaInstrInfo.cpp99 BuildMI(&MBB, DL, get(Alpha::BR)).addMBB(TBB); in InsertBranch()
102 BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_I)) in InsertBranch()
105 BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_F)) in InsertBranch()
112 BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_I)) in InsertBranch()
115 BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_F)) in InsertBranch()
117 BuildMI(&MBB, DL, get(Alpha::BR)).addMBB(FBB); in InsertBranch()
126 BuildMI(MBB, MI, DL, get(Alpha::BISr), DestReg) in copyPhysReg()
130 BuildMI(MBB, MI, DL, get(Alpha::CPYSS), DestReg) in copyPhysReg()
134 BuildMI(MBB, MI, DL, get(Alpha::CPYST), DestReg) in copyPhysReg()
156 BuildMI(MBB, MI, DL, get(Alpha::STS)) in storeRegToStackSlot()
[all …]
/external/llvm/lib/Target/Mips/
DMipsLongBranch.cpp225 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc); in replaceBranch()
298 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
300 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) in expandToLongBranch()
319 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT) in expandToLongBranch()
322 .append(BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB)) in expandToLongBranch()
323 .append(BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT) in expandToLongBranch()
330 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT) in expandToLongBranch()
332 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA) in expandToLongBranch()
337 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
341 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JALR)) in expandToLongBranch()
[all …]
DMipsSEFrameLowering.cpp159 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst) in expandLoadCCond()
173 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR) in expandStoreCCond()
197 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill); in expandLoadACC()
199 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill); in expandLoadACC()
219 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src); in expandStoreACC()
221 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandStoreACC()
252 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src); in expandCopyACC()
253 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo) in expandCopyACC()
255 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandCopyACC()
256 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi) in expandCopyACC()
[all …]
DMipsSEInstrInfo.cpp107 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4) in copyPhysReg()
128 BuildMI(MBB, I, DL, get(Mips::WRDSP)) in copyPhysReg()
133 BuildMI(MBB, I, DL, get(Mips::CTCMSA)) in copyPhysReg()
170 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); in copyPhysReg()
232 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0); in storeRegToStack()
235 BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64); in storeRegToStack()
238 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0); in storeRegToStack()
241 BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64); in storeRegToStack()
247 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) in storeRegToStack()
303 BuildMI(MBB, I, DL, get(Opc), DestReg) in loadRegFromStack()
[all …]
/external/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h242 inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, in BuildMI() function
249 inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, in BuildMI() function
258 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
274 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
284 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I, in BuildMI() function
290 return BuildMI(BB, MachineBasicBlock::instr_iterator(I), DL, MCID, DestReg); in BuildMI()
291 return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID, DestReg); in BuildMI()
294 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I, in BuildMI() function
297 return BuildMI(BB, *I, DL, MCID, DestReg); in BuildMI()
303 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCFrameLowering.cpp351 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
355 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
360 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
364 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
369 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
373 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
377 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
850 BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg); in emitPrologue()
853 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8)) in emitPrologue()
860 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg); in emitPrologue()
[all …]
DPPCRegisterInfo.cpp386 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) in lowerDynamicAlloc()
390 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) in lowerDynamicAlloc()
394 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) in lowerDynamicAlloc()
411 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg) in lowerDynamicAlloc()
416 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg) in lowerDynamicAlloc()
422 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) in lowerDynamicAlloc()
426 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) in lowerDynamicAlloc()
436 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg) in lowerDynamicAlloc()
441 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg) in lowerDynamicAlloc()
447 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) in lowerDynamicAlloc()
[all …]
/external/llvm/lib/Target/X86/
DX86FrameLowering.cpp272 BuildMI(MBB, MBBI, DL, TII.get(Opc), Reg) in emitSPUpdate()
277 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) in emitSPUpdate()
296 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc)) in emitSPUpdate()
349 MI = addRegOffset(BuildMI(MBB, MBBI, DL, in BuildStackAdjustment()
358 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) in BuildStackAdjustment()
420 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in BuildCFI()
585 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false, in emitStackProbeInline()
588 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false, in emitStackProbeInline()
593 BuildMI(&MBB, DL, TII.get(X86::MOV64rr), SizeReg).addReg(X86::RAX); in emitStackProbeInline()
598 BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg) in emitStackProbeInline()
[all …]
DX86ExpandPseudo.cpp112 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op)); in ExpandMI()
125 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op)); in ExpandMI()
129 BuildMI(MBB, MBBI, DL, in ExpandMI()
133 BuildMI(MBB, MBBI, DL, TII->get(X86::TAILJMPr)) in ExpandMI()
152 BuildMI(MBB, MBBI, DL, in ExpandMI()
163 BuildMI(MBB, MBBI, DL, in ExpandMI()
173 MIB = BuildMI(MBB, MBBI, DL, in ExpandMI()
176 MIB = BuildMI(MBB, MBBI, DL, in ExpandMI()
184 BuildMI(MBB, MBBI, DL, TII->get(X86::POP32r)).addReg(X86::ECX, RegState::Define); in ExpandMI()
186 BuildMI(MBB, MBBI, DL, TII->get(X86::PUSH32r)).addReg(X86::ECX); in ExpandMI()
[all …]
/external/llvm/lib/Target/Sparc/
DLeonPasses.cpp91 BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP)); in runOnMachineFunction()
99 BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP)); in runOnMachineFunction()
194 BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD)) in runOnMachineFunction()
199 BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD)) in runOnMachineFunction()
204 BuildMI(MBB, MBBI, DL, TII.get(SP::FMULD)) in runOnMachineFunction()
305 BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD)) in runOnMachineFunction()
310 BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD)) in runOnMachineFunction()
315 BuildMI(MBB, MBBI, DL, TII.get(SP::FMULD)) in runOnMachineFunction()
385 BuildMI(MBB, MBBI, DL, TII.get(SP::NOP)); in runOnMachineFunction()
390 BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP)); in runOnMachineFunction()
[all …]
DSparcInstrInfo.cpp254 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB); in InsertBranch()
262 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC); in InsertBranch()
264 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC); in InsertBranch()
268 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB); in InsertBranch()
319 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) in copyPhysReg()
327 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) in copyPhysReg()
331 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) in copyPhysReg()
342 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) in copyPhysReg()
358 BuildMI(MBB, I, DL, get(SP::WRASRrr), DestReg) in copyPhysReg()
363 BuildMI(MBB, I, DL, get(SP::RDASR), DestReg) in copyPhysReg()
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/external/llvm/lib/Target/AMDGPU/
DSILowerControlFlow.cpp207 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ)) in Skip()
225 BuildMI(&MBB, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ)) in skipIfDead()
231 BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::EXP)) in skipIfDead()
243 BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM)); in skipIfDead()
254 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg) in If()
257 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg) in If()
264 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::SI_MASK_BRANCH)) in If()
277 BuildMI(MBB, MBB.getFirstNonPHI(), DL, in Else()
285 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_B64), Dst) in Else()
290 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC) in Else()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/
DSparcInstrInfo.cpp194 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode)) in AnalyzeBranch()
196 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA)) in AnalyzeBranch()
229 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB); in InsertBranch()
237 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC); in InsertBranch()
239 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC); in InsertBranch()
243 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB); in InsertBranch()
274 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) in copyPhysReg()
277 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) in copyPhysReg()
280 BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD), DestReg) in copyPhysReg()
296 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0) in storeRegToStackSlot()
[all …]
/external/llvm/lib/Target/ARM/
DARMFrameLowering.cpp216 BuildMI(MBB, std::next(Info.I), dl, in emitDefCFAOffsets()
256 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg) in emitAligningInstructions()
261 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg) in emitAligningInstructions()
270 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
274 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
282 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg) in emitAligningInstructions()
451 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4) in emitPrologue()
455 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4) in emitPrologue()
464 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL)) in emitPrologue()
472 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12) in emitPrologue()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMFastISel.cpp283 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)); in FastEmitInst_()
294 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) in FastEmitInst_r()
297 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) in FastEmitInst_r()
299 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, in FastEmitInst_r()
314 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) in FastEmitInst_rr()
318 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) in FastEmitInst_rr()
321 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, in FastEmitInst_rr()
337 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) in FastEmitInst_rrr()
342 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) in FastEmitInst_rrr()
346 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, in FastEmitInst_rrr()
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430FrameLowering.cpp67 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r)) in emitPrologue()
71 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FP) in emitPrologue()
99 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SP) in emitPrologue()
136 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FP); in emitEpilogue()
157 BuildMI(MBB, MBBI, DL, in emitEpilogue()
161 BuildMI(MBB, MBBI, DL, in emitEpilogue()
171 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SP) in emitEpilogue()
200 BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r)) in spillCalleeSavedRegisters()
221 BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg()); in restoreCalleeSavedRegisters()
249 BuildMI(MF, Old.getDebugLoc(), TII.get(MSP430::SUB16ri), MSP430::SP) in eliminateCallFramePseudoInstr()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp552 MachineInstr *NewI = BuildMI(B, MI, DL, TII->get(Opc)); in createHalfInstr()
607 LowI = BuildMI(B, MI, DL, TII->get(Hexagon::L2_loadri_io), P.first) in splitMemRef()
610 HighI = BuildMI(B, MI, DL, TII->get(Hexagon::L2_loadri_io), P.second) in splitMemRef()
616 LowI = BuildMI(B, MI, DL, TII->get(Hexagon::S2_storeri_io)) in splitMemRef()
620 HighI = BuildMI(B, MI, DL, TII->get(Hexagon::S2_storeri_io)) in splitMemRef()
634 BuildMI(B, MI, DL, TII->get(Hexagon::A2_addi), NewR) in splitMemRef()
677 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.first) in splitImmediate()
679 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.second) in splitImmediate()
698 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.second) in splitCombine()
701 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.second) in splitCombine()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeFrameLowering.cpp257 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), r) in interruptFrameLayout()
265 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R17) in interruptFrameLayout()
268 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R18) in interruptFrameLayout()
274 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::MFS), MBlaze::R11) in interruptFrameLayout()
276 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R11) in interruptFrameLayout()
279 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R11) in interruptFrameLayout()
281 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::MTS), MBlaze::RMSR) in interruptFrameLayout()
286 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R18) in interruptFrameLayout()
289 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R17) in interruptFrameLayout()
295 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), r) in interruptFrameLayout()
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