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Searched refs:DIV_OP (Results 1 – 8 of 8) sorted by relevance

/external/v8/src/mips64/
Ddisasm-mips64.cc1307 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL()
1318 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL()
1329 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL()
1340 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL()
Dconstants-mips64.h471 DIV_OP = ((0U << 3) + 2), enumerator
Dassembler-mips64.cc1675 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD); in div()
1692 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD_U); in divu()
1729 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD); in ddiv()
1746 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD_U); in ddivu()
Dsimulator-mips64.cc3804 case DIV_OP: in DecodeTypeRegisterSPECIAL()
3834 case DIV_OP: in DecodeTypeRegisterSPECIAL()
3863 case DIV_OP: in DecodeTypeRegisterSPECIAL()
/external/v8/src/mips/
Ddisasm-mips.cc1135 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL()
1146 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL()
Dconstants-mips.h465 DIV_OP = ((0U << 3) + 2), enumerator
Dassembler-mips.cc1657 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD); in div()
1668 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD_U); in divu()
Dsimulator-mips.cc3803 case DIV_OP: in DecodeTypeRegisterSPECIAL()
3838 case DIV_OP: in DecodeTypeRegisterSPECIAL()