Searched refs:DIV_OP (Results 1 – 8 of 8) sorted by relevance
/external/v8/src/mips64/ |
D | disasm-mips64.cc | 1307 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL() 1318 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL() 1329 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL() 1340 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL()
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D | constants-mips64.h | 471 DIV_OP = ((0U << 3) + 2), enumerator
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D | assembler-mips64.cc | 1675 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD); in div() 1692 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD_U); in divu() 1729 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD); in ddiv() 1746 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD_U); in ddivu()
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D | simulator-mips64.cc | 3804 case DIV_OP: in DecodeTypeRegisterSPECIAL() 3834 case DIV_OP: in DecodeTypeRegisterSPECIAL() 3863 case DIV_OP: in DecodeTypeRegisterSPECIAL()
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/external/v8/src/mips/ |
D | disasm-mips.cc | 1135 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL() 1146 if (instr->SaValue() == DIV_OP) { in DecodeTypeRegisterSPECIAL()
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D | constants-mips.h | 465 DIV_OP = ((0U << 3) + 2), enumerator
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D | assembler-mips.cc | 1657 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD); in div() 1668 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD_U); in divu()
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D | simulator-mips.cc | 3803 case DIV_OP: in DecodeTypeRegisterSPECIAL() 3838 case DIV_OP: in DecodeTypeRegisterSPECIAL()
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