1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4
5 #ifndef V8_MIPS_CONSTANTS_H_
6 #define V8_MIPS_CONSTANTS_H_
7 #include "src/globals.h"
8 // UNIMPLEMENTED_ macro for MIPS.
9 #ifdef DEBUG
10 #define UNIMPLEMENTED_MIPS() \
11 v8::internal::PrintF("%s, \tline %d: \tfunction %s not implemented. \n", \
12 __FILE__, __LINE__, __func__)
13 #else
14 #define UNIMPLEMENTED_MIPS()
15 #endif
16
17 #define UNSUPPORTED_MIPS() v8::internal::PrintF("Unsupported instruction.\n")
18
19 enum ArchVariants {
20 kMips32r1 = v8::internal::MIPSr1,
21 kMips32r2 = v8::internal::MIPSr2,
22 kMips32r6 = v8::internal::MIPSr6,
23 kLoongson
24 };
25
26 #ifdef _MIPS_ARCH_MIPS32R2
27 static const ArchVariants kArchVariant = kMips32r2;
28 #elif _MIPS_ARCH_MIPS32R6
29 static const ArchVariants kArchVariant = kMips32r6;
30 #elif _MIPS_ARCH_LOONGSON
31 // The loongson flag refers to the LOONGSON architectures based on MIPS-III,
32 // which predates (and is a subset of) the mips32r2 and r1 architectures.
33 static const ArchVariants kArchVariant = kLoongson;
34 #elif _MIPS_ARCH_MIPS32RX
35 // This flags referred to compatibility mode that creates universal code that
36 // can run on any MIPS32 architecture revision. The dynamically generated code
37 // by v8 is specialized for the MIPS host detected in runtime probing.
38 static const ArchVariants kArchVariant = kMips32r1;
39 #else
40 static const ArchVariants kArchVariant = kMips32r1;
41 #endif
42
43 enum Endianness {
44 kLittle,
45 kBig
46 };
47
48 #if defined(V8_TARGET_LITTLE_ENDIAN)
49 static const Endianness kArchEndian = kLittle;
50 #elif defined(V8_TARGET_BIG_ENDIAN)
51 static const Endianness kArchEndian = kBig;
52 #else
53 #error Unknown endianness
54 #endif
55
56 enum FpuMode {
57 kFP32,
58 kFP64,
59 kFPXX
60 };
61
62 #if defined(FPU_MODE_FP32)
63 static const FpuMode kFpuMode = kFP32;
64 #elif defined(FPU_MODE_FP64)
65 static const FpuMode kFpuMode = kFP64;
66 #elif defined(FPU_MODE_FPXX)
67 #if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS32R6)
68 static const FpuMode kFpuMode = kFPXX;
69 #else
70 #error "FPXX is supported only on Mips32R2 and Mips32R6"
71 #endif
72 #else
73 static const FpuMode kFpuMode = kFP32;
74 #endif
75
76 #if(defined(__mips_hard_float) && __mips_hard_float != 0)
77 // Use floating-point coprocessor instructions. This flag is raised when
78 // -mhard-float is passed to the compiler.
79 const bool IsMipsSoftFloatABI = false;
80 #elif(defined(__mips_soft_float) && __mips_soft_float != 0)
81 // This flag is raised when -msoft-float is passed to the compiler.
82 // Although FPU is a base requirement for v8, soft-float ABI is used
83 // on soft-float systems with FPU kernel emulation.
84 const bool IsMipsSoftFloatABI = true;
85 #else
86 const bool IsMipsSoftFloatABI = true;
87 #endif
88
89 #if defined(V8_TARGET_LITTLE_ENDIAN)
90 const uint32_t kHoleNanUpper32Offset = 4;
91 const uint32_t kHoleNanLower32Offset = 0;
92 #elif defined(V8_TARGET_BIG_ENDIAN)
93 const uint32_t kHoleNanUpper32Offset = 0;
94 const uint32_t kHoleNanLower32Offset = 4;
95 #else
96 #error Unknown endianness
97 #endif
98
99 #define IsFp64Mode() (kFpuMode == kFP64)
100 #define IsFp32Mode() (kFpuMode == kFP32)
101 #define IsFpxxMode() (kFpuMode == kFPXX)
102
103 #ifndef _MIPS_ARCH_MIPS32RX
104 #define IsMipsArchVariant(check) \
105 (kArchVariant == check)
106 #else
107 #define IsMipsArchVariant(check) \
108 (CpuFeatures::IsSupported(static_cast<CpuFeature>(check)))
109 #endif
110
111 #if defined(V8_TARGET_LITTLE_ENDIAN)
112 const uint32_t kMipsLwrOffset = 0;
113 const uint32_t kMipsLwlOffset = 3;
114 const uint32_t kMipsSwrOffset = 0;
115 const uint32_t kMipsSwlOffset = 3;
116 #elif defined(V8_TARGET_BIG_ENDIAN)
117 const uint32_t kMipsLwrOffset = 3;
118 const uint32_t kMipsLwlOffset = 0;
119 const uint32_t kMipsSwrOffset = 3;
120 const uint32_t kMipsSwlOffset = 0;
121 #else
122 #error Unknown endianness
123 #endif
124
125 #define __STDC_FORMAT_MACROS
126 #include <inttypes.h>
127
128 // Defines constants and accessor classes to assemble, disassemble and
129 // simulate MIPS32 instructions.
130 //
131 // See: MIPS32 Architecture For Programmers
132 // Volume II: The MIPS32 Instruction Set
133 // Try www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf.
134
135 namespace v8 {
136 namespace internal {
137
138 // -----------------------------------------------------------------------------
139 // Registers and FPURegisters.
140
141 // Number of general purpose registers.
142 const int kNumRegisters = 32;
143 const int kInvalidRegister = -1;
144
145 // Number of registers with HI, LO, and pc.
146 const int kNumSimuRegisters = 35;
147
148 // In the simulator, the PC register is simulated as the 34th register.
149 const int kPCRegister = 34;
150
151 // Number coprocessor registers.
152 const int kNumFPURegisters = 32;
153 const int kInvalidFPURegister = -1;
154
155 // FPU (coprocessor 1) control registers. Currently only FCSR is implemented.
156 const int kFCSRRegister = 31;
157 const int kInvalidFPUControlRegister = -1;
158 const uint32_t kFPUInvalidResult = static_cast<uint32_t>(1 << 31) - 1;
159 const int32_t kFPUInvalidResultNegative = static_cast<int32_t>(1 << 31);
160 const uint64_t kFPU64InvalidResult =
161 static_cast<uint64_t>(static_cast<uint64_t>(1) << 63) - 1;
162 const int64_t kFPU64InvalidResultNegative =
163 static_cast<int64_t>(static_cast<uint64_t>(1) << 63);
164
165 // FCSR constants.
166 const uint32_t kFCSRInexactFlagBit = 2;
167 const uint32_t kFCSRUnderflowFlagBit = 3;
168 const uint32_t kFCSROverflowFlagBit = 4;
169 const uint32_t kFCSRDivideByZeroFlagBit = 5;
170 const uint32_t kFCSRInvalidOpFlagBit = 6;
171 const uint32_t kFCSRNaN2008FlagBit = 18;
172
173 const uint32_t kFCSRInexactFlagMask = 1 << kFCSRInexactFlagBit;
174 const uint32_t kFCSRUnderflowFlagMask = 1 << kFCSRUnderflowFlagBit;
175 const uint32_t kFCSROverflowFlagMask = 1 << kFCSROverflowFlagBit;
176 const uint32_t kFCSRDivideByZeroFlagMask = 1 << kFCSRDivideByZeroFlagBit;
177 const uint32_t kFCSRInvalidOpFlagMask = 1 << kFCSRInvalidOpFlagBit;
178 const uint32_t kFCSRNaN2008FlagMask = 1 << kFCSRNaN2008FlagBit;
179
180 const uint32_t kFCSRFlagMask =
181 kFCSRInexactFlagMask |
182 kFCSRUnderflowFlagMask |
183 kFCSROverflowFlagMask |
184 kFCSRDivideByZeroFlagMask |
185 kFCSRInvalidOpFlagMask;
186
187 const uint32_t kFCSRExceptionFlagMask = kFCSRFlagMask ^ kFCSRInexactFlagMask;
188
189 // 'pref' instruction hints
190 const int32_t kPrefHintLoad = 0;
191 const int32_t kPrefHintStore = 1;
192 const int32_t kPrefHintLoadStreamed = 4;
193 const int32_t kPrefHintStoreStreamed = 5;
194 const int32_t kPrefHintLoadRetained = 6;
195 const int32_t kPrefHintStoreRetained = 7;
196 const int32_t kPrefHintWritebackInvalidate = 25;
197 const int32_t kPrefHintPrepareForStore = 30;
198
199 // Helper functions for converting between register numbers and names.
200 class Registers {
201 public:
202 // Return the name of the register.
203 static const char* Name(int reg);
204
205 // Lookup the register number for the name provided.
206 static int Number(const char* name);
207
208 struct RegisterAlias {
209 int reg;
210 const char* name;
211 };
212
213 static const int32_t kMaxValue = 0x7fffffff;
214 static const int32_t kMinValue = 0x80000000;
215
216 private:
217 static const char* names_[kNumSimuRegisters];
218 static const RegisterAlias aliases_[];
219 };
220
221 // Helper functions for converting between register numbers and names.
222 class FPURegisters {
223 public:
224 // Return the name of the register.
225 static const char* Name(int reg);
226
227 // Lookup the register number for the name provided.
228 static int Number(const char* name);
229
230 struct RegisterAlias {
231 int creg;
232 const char* name;
233 };
234
235 private:
236 static const char* names_[kNumFPURegisters];
237 static const RegisterAlias aliases_[];
238 };
239
240
241 // -----------------------------------------------------------------------------
242 // Instructions encoding constants.
243
244 // On MIPS all instructions are 32 bits.
245 typedef int32_t Instr;
246
247 // Special Software Interrupt codes when used in the presence of the MIPS
248 // simulator.
249 enum SoftwareInterruptCodes {
250 // Transition to C code.
251 call_rt_redirected = 0xfffff
252 };
253
254 // On MIPS Simulator breakpoints can have different codes:
255 // - Breaks between 0 and kMaxWatchpointCode are treated as simple watchpoints,
256 // the simulator will run through them and print the registers.
257 // - Breaks between kMaxWatchpointCode and kMaxStopCode are treated as stop()
258 // instructions (see Assembler::stop()).
259 // - Breaks larger than kMaxStopCode are simple breaks, dropping you into the
260 // debugger.
261 const uint32_t kMaxWatchpointCode = 31;
262 const uint32_t kMaxStopCode = 127;
263 STATIC_ASSERT(kMaxWatchpointCode < kMaxStopCode);
264
265
266 // ----- Fields offset and length.
267 const int kOpcodeShift = 26;
268 const int kOpcodeBits = 6;
269 const int kRsShift = 21;
270 const int kRsBits = 5;
271 const int kRtShift = 16;
272 const int kRtBits = 5;
273 const int kRdShift = 11;
274 const int kRdBits = 5;
275 const int kSaShift = 6;
276 const int kSaBits = 5;
277 const int kLsaSaBits = 2;
278 const int kFunctionShift = 0;
279 const int kFunctionBits = 6;
280 const int kLuiShift = 16;
281 const int kBp2Shift = 6;
282 const int kBp2Bits = 2;
283
284 const int kImm16Shift = 0;
285 const int kImm16Bits = 16;
286 const int kImm18Shift = 0;
287 const int kImm18Bits = 18;
288 const int kImm19Shift = 0;
289 const int kImm19Bits = 19;
290 const int kImm21Shift = 0;
291 const int kImm21Bits = 21;
292 const int kImm26Shift = 0;
293 const int kImm26Bits = 26;
294 const int kImm28Shift = 0;
295 const int kImm28Bits = 28;
296 const int kImm32Shift = 0;
297 const int kImm32Bits = 32;
298
299 // In branches and jumps immediate fields point to words, not bytes,
300 // and are therefore shifted by 2.
301 const int kImmFieldShift = 2;
302
303 const int kFrBits = 5;
304 const int kFrShift = 21;
305 const int kFsShift = 11;
306 const int kFsBits = 5;
307 const int kFtShift = 16;
308 const int kFtBits = 5;
309 const int kFdShift = 6;
310 const int kFdBits = 5;
311 const int kFCccShift = 8;
312 const int kFCccBits = 3;
313 const int kFBccShift = 18;
314 const int kFBccBits = 3;
315 const int kFBtrueShift = 16;
316 const int kFBtrueBits = 1;
317
318 // ----- Miscellaneous useful masks.
319 // Instruction bit masks.
320 const int kOpcodeMask = ((1 << kOpcodeBits) - 1) << kOpcodeShift;
321 const int kImm16Mask = ((1 << kImm16Bits) - 1) << kImm16Shift;
322 const int kImm18Mask = ((1 << kImm18Bits) - 1) << kImm18Shift;
323 const int kImm19Mask = ((1 << kImm19Bits) - 1) << kImm19Shift;
324 const int kImm21Mask = ((1 << kImm21Bits) - 1) << kImm21Shift;
325 const int kImm26Mask = ((1 << kImm26Bits) - 1) << kImm26Shift;
326 const int kImm28Mask = ((1 << kImm28Bits) - 1) << kImm28Shift;
327 const int kRsFieldMask = ((1 << kRsBits) - 1) << kRsShift;
328 const int kRtFieldMask = ((1 << kRtBits) - 1) << kRtShift;
329 const int kRdFieldMask = ((1 << kRdBits) - 1) << kRdShift;
330 const int kSaFieldMask = ((1 << kSaBits) - 1) << kSaShift;
331 const int kFunctionFieldMask = ((1 << kFunctionBits) - 1) << kFunctionShift;
332 // Misc masks.
333 const int kHiMask = 0xffff << 16;
334 const int kLoMask = 0xffff;
335 const int kSignMask = 0x80000000;
336 const int kJumpAddrMask = (1 << (kImm26Bits + kImmFieldShift)) - 1;
337
338 // ----- MIPS Opcodes and Function Fields.
339 // We use this presentation to stay close to the table representation in
340 // MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set.
341 enum Opcode : uint32_t {
342 SPECIAL = 0U << kOpcodeShift,
343 REGIMM = 1U << kOpcodeShift,
344
345 J = ((0U << 3) + 2) << kOpcodeShift,
346 JAL = ((0U << 3) + 3) << kOpcodeShift,
347 BEQ = ((0U << 3) + 4) << kOpcodeShift,
348 BNE = ((0U << 3) + 5) << kOpcodeShift,
349 BLEZ = ((0U << 3) + 6) << kOpcodeShift,
350 BGTZ = ((0U << 3) + 7) << kOpcodeShift,
351
352 ADDI = ((1U << 3) + 0) << kOpcodeShift,
353 ADDIU = ((1U << 3) + 1) << kOpcodeShift,
354 SLTI = ((1U << 3) + 2) << kOpcodeShift,
355 SLTIU = ((1U << 3) + 3) << kOpcodeShift,
356 ANDI = ((1U << 3) + 4) << kOpcodeShift,
357 ORI = ((1U << 3) + 5) << kOpcodeShift,
358 XORI = ((1U << 3) + 6) << kOpcodeShift,
359 LUI = ((1U << 3) + 7) << kOpcodeShift, // LUI/AUI family.
360
361 BEQC = ((2U << 3) + 0) << kOpcodeShift,
362 COP1 = ((2U << 3) + 1) << kOpcodeShift, // Coprocessor 1 class.
363 BEQL = ((2U << 3) + 4) << kOpcodeShift,
364 BNEL = ((2U << 3) + 5) << kOpcodeShift,
365 BLEZL = ((2U << 3) + 6) << kOpcodeShift,
366 BGTZL = ((2U << 3) + 7) << kOpcodeShift,
367
368 DADDI = ((3U << 3) + 0) << kOpcodeShift, // This is also BNEC.
369 SPECIAL2 = ((3U << 3) + 4) << kOpcodeShift,
370 SPECIAL3 = ((3U << 3) + 7) << kOpcodeShift,
371
372 LB = ((4U << 3) + 0) << kOpcodeShift,
373 LH = ((4U << 3) + 1) << kOpcodeShift,
374 LWL = ((4U << 3) + 2) << kOpcodeShift,
375 LW = ((4U << 3) + 3) << kOpcodeShift,
376 LBU = ((4U << 3) + 4) << kOpcodeShift,
377 LHU = ((4U << 3) + 5) << kOpcodeShift,
378 LWR = ((4U << 3) + 6) << kOpcodeShift,
379 SB = ((5U << 3) + 0) << kOpcodeShift,
380 SH = ((5U << 3) + 1) << kOpcodeShift,
381 SWL = ((5U << 3) + 2) << kOpcodeShift,
382 SW = ((5U << 3) + 3) << kOpcodeShift,
383 SWR = ((5U << 3) + 6) << kOpcodeShift,
384
385 LWC1 = ((6U << 3) + 1) << kOpcodeShift,
386 BC = ((6U << 3) + 2) << kOpcodeShift,
387 LDC1 = ((6U << 3) + 5) << kOpcodeShift,
388 POP66 = ((6U << 3) + 6) << kOpcodeShift, // beqzc, jic
389
390 PREF = ((6U << 3) + 3) << kOpcodeShift,
391
392 SWC1 = ((7U << 3) + 1) << kOpcodeShift,
393 BALC = ((7U << 3) + 2) << kOpcodeShift,
394 PCREL = ((7U << 3) + 3) << kOpcodeShift,
395 SDC1 = ((7U << 3) + 5) << kOpcodeShift,
396 POP76 = ((7U << 3) + 6) << kOpcodeShift, // bnezc, jialc
397
398 COP1X = ((1U << 4) + 3) << kOpcodeShift,
399
400 // New r6 instruction.
401 POP06 = BLEZ, // bgeuc/bleuc, blezalc, bgezalc
402 POP07 = BGTZ, // bltuc/bgtuc, bgtzalc, bltzalc
403 POP10 = ADDI, // beqzalc, bovc, beqc
404 POP26 = BLEZL, // bgezc, blezc, bgec/blec
405 POP27 = BGTZL, // bgtzc, bltzc, bltc/bgtc
406 POP30 = DADDI, // bnezalc, bnvc, bnec
407 };
408
409 enum SecondaryField : uint32_t {
410 // SPECIAL Encoding of Function Field.
411 SLL = ((0U << 3) + 0),
412 MOVCI = ((0U << 3) + 1),
413 SRL = ((0U << 3) + 2),
414 SRA = ((0U << 3) + 3),
415 SLLV = ((0U << 3) + 4),
416 LSA = ((0U << 3) + 5),
417 SRLV = ((0U << 3) + 6),
418 SRAV = ((0U << 3) + 7),
419
420 JR = ((1U << 3) + 0),
421 JALR = ((1U << 3) + 1),
422 MOVZ = ((1U << 3) + 2),
423 MOVN = ((1U << 3) + 3),
424 BREAK = ((1U << 3) + 5),
425 SYNC = ((1U << 3) + 7),
426
427 MFHI = ((2U << 3) + 0),
428 CLZ_R6 = ((2U << 3) + 0),
429 CLO_R6 = ((2U << 3) + 1),
430 MFLO = ((2U << 3) + 2),
431
432 MULT = ((3U << 3) + 0),
433 MULTU = ((3U << 3) + 1),
434 DIV = ((3U << 3) + 2),
435 DIVU = ((3U << 3) + 3),
436
437 ADD = ((4U << 3) + 0),
438 ADDU = ((4U << 3) + 1),
439 SUB = ((4U << 3) + 2),
440 SUBU = ((4U << 3) + 3),
441 AND = ((4U << 3) + 4),
442 OR = ((4U << 3) + 5),
443 XOR = ((4U << 3) + 6),
444 NOR = ((4U << 3) + 7),
445
446 SLT = ((5U << 3) + 2),
447 SLTU = ((5U << 3) + 3),
448
449 TGE = ((6U << 3) + 0),
450 TGEU = ((6U << 3) + 1),
451 TLT = ((6U << 3) + 2),
452 TLTU = ((6U << 3) + 3),
453 TEQ = ((6U << 3) + 4),
454 SELEQZ_S = ((6U << 3) + 5),
455 TNE = ((6U << 3) + 6),
456 SELNEZ_S = ((6U << 3) + 7),
457
458 // Multiply integers in r6.
459 MUL_MUH = ((3U << 3) + 0), // MUL, MUH.
460 MUL_MUH_U = ((3U << 3) + 1), // MUL_U, MUH_U.
461 RINT = ((3U << 3) + 2),
462
463 MUL_OP = ((0U << 3) + 2),
464 MUH_OP = ((0U << 3) + 3),
465 DIV_OP = ((0U << 3) + 2),
466 MOD_OP = ((0U << 3) + 3),
467
468 DIV_MOD = ((3U << 3) + 2),
469 DIV_MOD_U = ((3U << 3) + 3),
470
471 // SPECIAL2 Encoding of Function Field.
472 MUL = ((0U << 3) + 2),
473 CLZ = ((4U << 3) + 0),
474 CLO = ((4U << 3) + 1),
475
476 // SPECIAL3 Encoding of Function Field.
477 EXT = ((0U << 3) + 0),
478 INS = ((0U << 3) + 4),
479 BSHFL = ((4U << 3) + 0),
480
481 // SPECIAL3 Encoding of sa Field.
482 BITSWAP = ((0U << 3) + 0),
483 ALIGN = ((0U << 3) + 2),
484 WSBH = ((0U << 3) + 2),
485 SEB = ((2U << 3) + 0),
486 SEH = ((3U << 3) + 0),
487
488 // REGIMM encoding of rt Field.
489 BLTZ = ((0U << 3) + 0) << 16,
490 BGEZ = ((0U << 3) + 1) << 16,
491 BLTZAL = ((2U << 3) + 0) << 16,
492 BGEZAL = ((2U << 3) + 1) << 16,
493 BGEZALL = ((2U << 3) + 3) << 16,
494
495 // COP1 Encoding of rs Field.
496 MFC1 = ((0U << 3) + 0) << 21,
497 CFC1 = ((0U << 3) + 2) << 21,
498 MFHC1 = ((0U << 3) + 3) << 21,
499 MTC1 = ((0U << 3) + 4) << 21,
500 CTC1 = ((0U << 3) + 6) << 21,
501 MTHC1 = ((0U << 3) + 7) << 21,
502 BC1 = ((1U << 3) + 0) << 21,
503 S = ((2U << 3) + 0) << 21,
504 D = ((2U << 3) + 1) << 21,
505 W = ((2U << 3) + 4) << 21,
506 L = ((2U << 3) + 5) << 21,
507 PS = ((2U << 3) + 6) << 21,
508 // COP1 Encoding of Function Field When rs=S.
509
510 ADD_S = ((0U << 3) + 0),
511 SUB_S = ((0U << 3) + 1),
512 MUL_S = ((0U << 3) + 2),
513 DIV_S = ((0U << 3) + 3),
514 ABS_S = ((0U << 3) + 5),
515 SQRT_S = ((0U << 3) + 4),
516 MOV_S = ((0U << 3) + 6),
517 NEG_S = ((0U << 3) + 7),
518 ROUND_L_S = ((1U << 3) + 0),
519 TRUNC_L_S = ((1U << 3) + 1),
520 CEIL_L_S = ((1U << 3) + 2),
521 FLOOR_L_S = ((1U << 3) + 3),
522 ROUND_W_S = ((1U << 3) + 4),
523 TRUNC_W_S = ((1U << 3) + 5),
524 CEIL_W_S = ((1U << 3) + 6),
525 FLOOR_W_S = ((1U << 3) + 7),
526 RECIP_S = ((2U << 3) + 5),
527 RSQRT_S = ((2U << 3) + 6),
528 MADDF_S = ((3U << 3) + 0),
529 MSUBF_S = ((3U << 3) + 1),
530 CLASS_S = ((3U << 3) + 3),
531 CVT_D_S = ((4U << 3) + 1),
532 CVT_W_S = ((4U << 3) + 4),
533 CVT_L_S = ((4U << 3) + 5),
534 CVT_PS_S = ((4U << 3) + 6),
535
536 // COP1 Encoding of Function Field When rs=D.
537 ADD_D = ((0U << 3) + 0),
538 SUB_D = ((0U << 3) + 1),
539 MUL_D = ((0U << 3) + 2),
540 DIV_D = ((0U << 3) + 3),
541 SQRT_D = ((0U << 3) + 4),
542 ABS_D = ((0U << 3) + 5),
543 MOV_D = ((0U << 3) + 6),
544 NEG_D = ((0U << 3) + 7),
545 ROUND_L_D = ((1U << 3) + 0),
546 TRUNC_L_D = ((1U << 3) + 1),
547 CEIL_L_D = ((1U << 3) + 2),
548 FLOOR_L_D = ((1U << 3) + 3),
549 ROUND_W_D = ((1U << 3) + 4),
550 TRUNC_W_D = ((1U << 3) + 5),
551 CEIL_W_D = ((1U << 3) + 6),
552 FLOOR_W_D = ((1U << 3) + 7),
553 RECIP_D = ((2U << 3) + 5),
554 RSQRT_D = ((2U << 3) + 6),
555 MADDF_D = ((3U << 3) + 0),
556 MSUBF_D = ((3U << 3) + 1),
557 CLASS_D = ((3U << 3) + 3),
558 MIN = ((3U << 3) + 4),
559 MINA = ((3U << 3) + 5),
560 MAX = ((3U << 3) + 6),
561 MAXA = ((3U << 3) + 7),
562 CVT_S_D = ((4U << 3) + 0),
563 CVT_W_D = ((4U << 3) + 4),
564 CVT_L_D = ((4U << 3) + 5),
565 C_F_D = ((6U << 3) + 0),
566 C_UN_D = ((6U << 3) + 1),
567 C_EQ_D = ((6U << 3) + 2),
568 C_UEQ_D = ((6U << 3) + 3),
569 C_OLT_D = ((6U << 3) + 4),
570 C_ULT_D = ((6U << 3) + 5),
571 C_OLE_D = ((6U << 3) + 6),
572 C_ULE_D = ((6U << 3) + 7),
573
574 // COP1 Encoding of Function Field When rs=W or L.
575 CVT_S_W = ((4U << 3) + 0),
576 CVT_D_W = ((4U << 3) + 1),
577 CVT_S_L = ((4U << 3) + 0),
578 CVT_D_L = ((4U << 3) + 1),
579 BC1EQZ = ((2U << 2) + 1) << 21,
580 BC1NEZ = ((3U << 2) + 1) << 21,
581 // COP1 CMP positive predicates Bit 5..4 = 00.
582 CMP_AF = ((0U << 3) + 0),
583 CMP_UN = ((0U << 3) + 1),
584 CMP_EQ = ((0U << 3) + 2),
585 CMP_UEQ = ((0U << 3) + 3),
586 CMP_LT = ((0U << 3) + 4),
587 CMP_ULT = ((0U << 3) + 5),
588 CMP_LE = ((0U << 3) + 6),
589 CMP_ULE = ((0U << 3) + 7),
590 CMP_SAF = ((1U << 3) + 0),
591 CMP_SUN = ((1U << 3) + 1),
592 CMP_SEQ = ((1U << 3) + 2),
593 CMP_SUEQ = ((1U << 3) + 3),
594 CMP_SSLT = ((1U << 3) + 4),
595 CMP_SSULT = ((1U << 3) + 5),
596 CMP_SLE = ((1U << 3) + 6),
597 CMP_SULE = ((1U << 3) + 7),
598 // COP1 CMP negative predicates Bit 5..4 = 01.
599 CMP_AT = ((2U << 3) + 0), // Reserved, not implemented.
600 CMP_OR = ((2U << 3) + 1),
601 CMP_UNE = ((2U << 3) + 2),
602 CMP_NE = ((2U << 3) + 3),
603 CMP_UGE = ((2U << 3) + 4), // Reserved, not implemented.
604 CMP_OGE = ((2U << 3) + 5), // Reserved, not implemented.
605 CMP_UGT = ((2U << 3) + 6), // Reserved, not implemented.
606 CMP_OGT = ((2U << 3) + 7), // Reserved, not implemented.
607 CMP_SAT = ((3U << 3) + 0), // Reserved, not implemented.
608 CMP_SOR = ((3U << 3) + 1),
609 CMP_SUNE = ((3U << 3) + 2),
610 CMP_SNE = ((3U << 3) + 3),
611 CMP_SUGE = ((3U << 3) + 4), // Reserved, not implemented.
612 CMP_SOGE = ((3U << 3) + 5), // Reserved, not implemented.
613 CMP_SUGT = ((3U << 3) + 6), // Reserved, not implemented.
614 CMP_SOGT = ((3U << 3) + 7), // Reserved, not implemented.
615
616 SEL = ((2U << 3) + 0),
617 MOVZ_C = ((2U << 3) + 2),
618 MOVN_C = ((2U << 3) + 3),
619 SELEQZ_C = ((2U << 3) + 4), // COP1 on FPR registers.
620 MOVF = ((2U << 3) + 1), // Function field for MOVT.fmt and MOVF.fmt
621 SELNEZ_C = ((2U << 3) + 7), // COP1 on FPR registers.
622 // COP1 Encoding of Function Field When rs=PS.
623
624 // COP1X Encoding of Function Field.
625 MADD_S = ((4U << 3) + 0),
626 MADD_D = ((4U << 3) + 1),
627 MSUB_S = ((5U << 3) + 0),
628 MSUB_D = ((5U << 3) + 1),
629
630 // PCREL Encoding of rt Field.
631 ADDIUPC = ((0U << 2) + 0),
632 LWPC = ((0U << 2) + 1),
633 AUIPC = ((3U << 3) + 6),
634 ALUIPC = ((3U << 3) + 7),
635
636 // POP66 Encoding of rs Field.
637 JIC = ((0U << 5) + 0),
638
639 // POP76 Encoding of rs Field.
640 JIALC = ((0U << 5) + 0),
641
642 NULLSF = 0U
643 };
644
645 // ----- Emulated conditions.
646 // On MIPS we use this enum to abstract from conditional branch instructions.
647 // The 'U' prefix is used to specify unsigned comparisons.
648 // Opposite conditions must be paired as odd/even numbers
649 // because 'NegateCondition' function flips LSB to negate condition.
650 enum Condition {
651 // Any value < 0 is considered no_condition.
652 kNoCondition = -1,
653 overflow = 0,
654 no_overflow = 1,
655 Uless = 2,
656 Ugreater_equal = 3,
657 Uless_equal = 4,
658 Ugreater = 5,
659 equal = 6,
660 not_equal = 7, // Unordered or Not Equal.
661 negative = 8,
662 positive = 9,
663 parity_even = 10,
664 parity_odd = 11,
665 less = 12,
666 greater_equal = 13,
667 less_equal = 14,
668 greater = 15,
669 ueq = 16, // Unordered or Equal.
670 ogl = 17, // Ordered and Not Equal.
671 cc_always = 18,
672
673 // Aliases.
674 carry = Uless,
675 not_carry = Ugreater_equal,
676 zero = equal,
677 eq = equal,
678 not_zero = not_equal,
679 ne = not_equal,
680 nz = not_equal,
681 sign = negative,
682 not_sign = positive,
683 mi = negative,
684 pl = positive,
685 hi = Ugreater,
686 ls = Uless_equal,
687 ge = greater_equal,
688 lt = less,
689 gt = greater,
690 le = less_equal,
691 hs = Ugreater_equal,
692 lo = Uless,
693 al = cc_always,
694 ult = Uless,
695 uge = Ugreater_equal,
696 ule = Uless_equal,
697 ugt = Ugreater,
698 cc_default = kNoCondition
699 };
700
701
702 // Returns the equivalent of !cc.
703 // Negation of the default kNoCondition (-1) results in a non-default
704 // no_condition value (-2). As long as tests for no_condition check
705 // for condition < 0, this will work as expected.
NegateCondition(Condition cc)706 inline Condition NegateCondition(Condition cc) {
707 DCHECK(cc != cc_always);
708 return static_cast<Condition>(cc ^ 1);
709 }
710
711
NegateFpuCondition(Condition cc)712 inline Condition NegateFpuCondition(Condition cc) {
713 DCHECK(cc != cc_always);
714 switch (cc) {
715 case ult:
716 return ge;
717 case ugt:
718 return le;
719 case uge:
720 return lt;
721 case ule:
722 return gt;
723 case lt:
724 return uge;
725 case gt:
726 return ule;
727 case ge:
728 return ult;
729 case le:
730 return ugt;
731 case eq:
732 return ne;
733 case ne:
734 return eq;
735 case ueq:
736 return ogl;
737 case ogl:
738 return ueq;
739 default:
740 return cc;
741 }
742 }
743
744
745 // Commute a condition such that {a cond b == b cond' a}.
CommuteCondition(Condition cc)746 inline Condition CommuteCondition(Condition cc) {
747 switch (cc) {
748 case Uless:
749 return Ugreater;
750 case Ugreater:
751 return Uless;
752 case Ugreater_equal:
753 return Uless_equal;
754 case Uless_equal:
755 return Ugreater_equal;
756 case less:
757 return greater;
758 case greater:
759 return less;
760 case greater_equal:
761 return less_equal;
762 case less_equal:
763 return greater_equal;
764 default:
765 return cc;
766 }
767 }
768
769
770 // ----- Coprocessor conditions.
771 enum FPUCondition {
772 kNoFPUCondition = -1,
773
774 F = 0x00, // False.
775 UN = 0x01, // Unordered.
776 EQ = 0x02, // Equal.
777 UEQ = 0x03, // Unordered or Equal.
778 OLT = 0x04, // Ordered or Less Than, on Mips release < 6.
779 LT = 0x04, // Ordered or Less Than, on Mips release >= 6.
780 ULT = 0x05, // Unordered or Less Than.
781 OLE = 0x06, // Ordered or Less Than or Equal, on Mips release < 6.
782 LE = 0x06, // Ordered or Less Than or Equal, on Mips release >= 6.
783 ULE = 0x07, // Unordered or Less Than or Equal.
784
785 // Following constants are available on Mips release >= 6 only.
786 ORD = 0x11, // Ordered, on Mips release >= 6.
787 UNE = 0x12, // Not equal, on Mips release >= 6.
788 NE = 0x13, // Ordered Greater Than or Less Than. on Mips >= 6 only.
789 };
790
791
792 // FPU rounding modes.
793 enum FPURoundingMode {
794 RN = 0 << 0, // Round to Nearest.
795 RZ = 1 << 0, // Round towards zero.
796 RP = 2 << 0, // Round towards Plus Infinity.
797 RM = 3 << 0, // Round towards Minus Infinity.
798
799 // Aliases.
800 kRoundToNearest = RN,
801 kRoundToZero = RZ,
802 kRoundToPlusInf = RP,
803 kRoundToMinusInf = RM,
804
805 mode_round = RN,
806 mode_ceil = RP,
807 mode_floor = RM,
808 mode_trunc = RZ
809 };
810
811 const uint32_t kFPURoundingModeMask = 3 << 0;
812
813 enum CheckForInexactConversion {
814 kCheckForInexactConversion,
815 kDontCheckForInexactConversion
816 };
817
818 enum class MaxMinKind : int { kMin = 0, kMax = 1 };
819
820 // -----------------------------------------------------------------------------
821 // Hints.
822
823 // Branch hints are not used on the MIPS. They are defined so that they can
824 // appear in shared function signatures, but will be ignored in MIPS
825 // implementations.
826 enum Hint {
827 no_hint = 0
828 };
829
830
NegateHint(Hint hint)831 inline Hint NegateHint(Hint hint) {
832 return no_hint;
833 }
834
835
836 // -----------------------------------------------------------------------------
837 // Specific instructions, constants, and masks.
838 // These constants are declared in assembler-mips.cc, as they use named
839 // registers and other constants.
840
841 // addiu(sp, sp, 4) aka Pop() operation or part of Pop(r)
842 // operations as post-increment of sp.
843 extern const Instr kPopInstruction;
844 // addiu(sp, sp, -4) part of Push(r) operation as pre-decrement of sp.
845 extern const Instr kPushInstruction;
846 // sw(r, MemOperand(sp, 0))
847 extern const Instr kPushRegPattern;
848 // lw(r, MemOperand(sp, 0))
849 extern const Instr kPopRegPattern;
850 extern const Instr kLwRegFpOffsetPattern;
851 extern const Instr kSwRegFpOffsetPattern;
852 extern const Instr kLwRegFpNegOffsetPattern;
853 extern const Instr kSwRegFpNegOffsetPattern;
854 // A mask for the Rt register for push, pop, lw, sw instructions.
855 extern const Instr kRtMask;
856 extern const Instr kLwSwInstrTypeMask;
857 extern const Instr kLwSwInstrArgumentMask;
858 extern const Instr kLwSwOffsetMask;
859
860 // Break 0xfffff, reserved for redirected real time call.
861 const Instr rtCallRedirInstr = SPECIAL | BREAK | call_rt_redirected << 6;
862 // A nop instruction. (Encoding of sll 0 0 0).
863 const Instr nopInstr = 0;
864
OpcodeToBitNumber(Opcode opcode)865 static constexpr uint64_t OpcodeToBitNumber(Opcode opcode) {
866 return 1ULL << (static_cast<uint32_t>(opcode) >> kOpcodeShift);
867 }
868
869 class InstructionBase {
870 public:
871 enum {
872 kInstrSize = 4,
873 kInstrSizeLog2 = 2,
874 // On MIPS PC cannot actually be directly accessed. We behave as if PC was
875 // always the value of the current instruction being executed.
876 kPCReadOffset = 0
877 };
878
879 // Instruction type.
880 enum Type { kRegisterType, kImmediateType, kJumpType, kUnsupported = -1 };
881
882 // Get the raw instruction bits.
InstructionBits()883 inline Instr InstructionBits() const {
884 return *reinterpret_cast<const Instr*>(this);
885 }
886
887 // Set the raw instruction bits to value.
SetInstructionBits(Instr value)888 inline void SetInstructionBits(Instr value) {
889 *reinterpret_cast<Instr*>(this) = value;
890 }
891
892 // Read one particular bit out of the instruction bits.
Bit(int nr)893 inline int Bit(int nr) const {
894 return (InstructionBits() >> nr) & 1;
895 }
896
897 // Read a bit field out of the instruction bits.
Bits(int hi,int lo)898 inline int Bits(int hi, int lo) const {
899 return (InstructionBits() >> lo) & ((2U << (hi - lo)) - 1);
900 }
901
902
903 static constexpr uint64_t kOpcodeImmediateTypeMask =
904 OpcodeToBitNumber(REGIMM) | OpcodeToBitNumber(BEQ) |
905 OpcodeToBitNumber(BNE) | OpcodeToBitNumber(BLEZ) |
906 OpcodeToBitNumber(BGTZ) | OpcodeToBitNumber(ADDI) |
907 OpcodeToBitNumber(DADDI) | OpcodeToBitNumber(ADDIU) |
908 OpcodeToBitNumber(SLTI) | OpcodeToBitNumber(SLTIU) |
909 OpcodeToBitNumber(ANDI) | OpcodeToBitNumber(ORI) |
910 OpcodeToBitNumber(XORI) | OpcodeToBitNumber(LUI) |
911 OpcodeToBitNumber(BEQL) | OpcodeToBitNumber(BNEL) |
912 OpcodeToBitNumber(BLEZL) | OpcodeToBitNumber(BGTZL) |
913 OpcodeToBitNumber(POP66) | OpcodeToBitNumber(POP76) |
914 OpcodeToBitNumber(LB) | OpcodeToBitNumber(LH) | OpcodeToBitNumber(LWL) |
915 OpcodeToBitNumber(LW) | OpcodeToBitNumber(LBU) | OpcodeToBitNumber(LHU) |
916 OpcodeToBitNumber(LWR) | OpcodeToBitNumber(SB) | OpcodeToBitNumber(SH) |
917 OpcodeToBitNumber(SWL) | OpcodeToBitNumber(SW) | OpcodeToBitNumber(SWR) |
918 OpcodeToBitNumber(LWC1) | OpcodeToBitNumber(LDC1) |
919 OpcodeToBitNumber(SWC1) | OpcodeToBitNumber(SDC1) |
920 OpcodeToBitNumber(PCREL) | OpcodeToBitNumber(BC) |
921 OpcodeToBitNumber(BALC);
922
923 #define FunctionFieldToBitNumber(function) (1ULL << function)
924
925 static const uint64_t kFunctionFieldRegisterTypeMask =
926 FunctionFieldToBitNumber(JR) | FunctionFieldToBitNumber(JALR) |
927 FunctionFieldToBitNumber(BREAK) | FunctionFieldToBitNumber(SLL) |
928 FunctionFieldToBitNumber(SRL) | FunctionFieldToBitNumber(SRA) |
929 FunctionFieldToBitNumber(SLLV) | FunctionFieldToBitNumber(SRLV) |
930 FunctionFieldToBitNumber(SRAV) | FunctionFieldToBitNumber(LSA) |
931 FunctionFieldToBitNumber(MFHI) | FunctionFieldToBitNumber(MFLO) |
932 FunctionFieldToBitNumber(MULT) | FunctionFieldToBitNumber(MULTU) |
933 FunctionFieldToBitNumber(DIV) | FunctionFieldToBitNumber(DIVU) |
934 FunctionFieldToBitNumber(ADD) | FunctionFieldToBitNumber(ADDU) |
935 FunctionFieldToBitNumber(SUB) | FunctionFieldToBitNumber(SUBU) |
936 FunctionFieldToBitNumber(AND) | FunctionFieldToBitNumber(OR) |
937 FunctionFieldToBitNumber(XOR) | FunctionFieldToBitNumber(NOR) |
938 FunctionFieldToBitNumber(SLT) | FunctionFieldToBitNumber(SLTU) |
939 FunctionFieldToBitNumber(TGE) | FunctionFieldToBitNumber(TGEU) |
940 FunctionFieldToBitNumber(TLT) | FunctionFieldToBitNumber(TLTU) |
941 FunctionFieldToBitNumber(TEQ) | FunctionFieldToBitNumber(TNE) |
942 FunctionFieldToBitNumber(MOVZ) | FunctionFieldToBitNumber(MOVN) |
943 FunctionFieldToBitNumber(MOVCI) | FunctionFieldToBitNumber(SELEQZ_S) |
944 FunctionFieldToBitNumber(SELNEZ_S) | FunctionFieldToBitNumber(SYNC);
945
946 // Accessors for the different named fields used in the MIPS encoding.
OpcodeValue()947 inline Opcode OpcodeValue() const {
948 return static_cast<Opcode>(
949 Bits(kOpcodeShift + kOpcodeBits - 1, kOpcodeShift));
950 }
951
FunctionFieldRaw()952 inline int FunctionFieldRaw() const {
953 return InstructionBits() & kFunctionFieldMask;
954 }
955
956 // Return the fields at their original place in the instruction encoding.
OpcodeFieldRaw()957 inline Opcode OpcodeFieldRaw() const {
958 return static_cast<Opcode>(InstructionBits() & kOpcodeMask);
959 }
960
961 // Safe to call within InstructionType().
RsFieldRawNoAssert()962 inline int RsFieldRawNoAssert() const {
963 return InstructionBits() & kRsFieldMask;
964 }
965
SaFieldRaw()966 inline int SaFieldRaw() const { return InstructionBits() & kSaFieldMask; }
967
968 // Get the encoding type of the instruction.
969 inline Type InstructionType() const;
970
971 protected:
InstructionBase()972 InstructionBase() {}
973 };
974
975 template <class T>
976 class InstructionGetters : public T {
977 public:
RsValue()978 inline int RsValue() const {
979 DCHECK(this->InstructionType() == InstructionBase::kRegisterType ||
980 this->InstructionType() == InstructionBase::kImmediateType);
981 return InstructionBase::Bits(kRsShift + kRsBits - 1, kRsShift);
982 }
983
RtValue()984 inline int RtValue() const {
985 DCHECK(this->InstructionType() == InstructionBase::kRegisterType ||
986 this->InstructionType() == InstructionBase::kImmediateType);
987 return this->Bits(kRtShift + kRtBits - 1, kRtShift);
988 }
989
RdValue()990 inline int RdValue() const {
991 DCHECK(this->InstructionType() == InstructionBase::kRegisterType);
992 return this->Bits(kRdShift + kRdBits - 1, kRdShift);
993 }
994
SaValue()995 inline int SaValue() const {
996 DCHECK(this->InstructionType() == InstructionBase::kRegisterType);
997 return this->Bits(kSaShift + kSaBits - 1, kSaShift);
998 }
999
LsaSaValue()1000 inline int LsaSaValue() const {
1001 DCHECK(this->InstructionType() == InstructionBase::kRegisterType);
1002 return this->Bits(kSaShift + kLsaSaBits - 1, kSaShift);
1003 }
1004
FunctionValue()1005 inline int FunctionValue() const {
1006 DCHECK(this->InstructionType() == InstructionBase::kRegisterType ||
1007 this->InstructionType() == InstructionBase::kImmediateType);
1008 return this->Bits(kFunctionShift + kFunctionBits - 1, kFunctionShift);
1009 }
1010
FdValue()1011 inline int FdValue() const {
1012 return this->Bits(kFdShift + kFdBits - 1, kFdShift);
1013 }
1014
FsValue()1015 inline int FsValue() const {
1016 return this->Bits(kFsShift + kFsBits - 1, kFsShift);
1017 }
1018
FtValue()1019 inline int FtValue() const {
1020 return this->Bits(kFtShift + kFtBits - 1, kFtShift);
1021 }
1022
FrValue()1023 inline int FrValue() const {
1024 return this->Bits(kFrShift + kFrBits - 1, kFrShift);
1025 }
1026
Bp2Value()1027 inline int Bp2Value() const {
1028 DCHECK(this->InstructionType() == InstructionBase::kRegisterType);
1029 return this->Bits(kBp2Shift + kBp2Bits - 1, kBp2Shift);
1030 }
1031
1032 // Float Compare condition code instruction bits.
FCccValue()1033 inline int FCccValue() const {
1034 return this->Bits(kFCccShift + kFCccBits - 1, kFCccShift);
1035 }
1036
1037 // Float Branch condition code instruction bits.
FBccValue()1038 inline int FBccValue() const {
1039 return this->Bits(kFBccShift + kFBccBits - 1, kFBccShift);
1040 }
1041
1042 // Float Branch true/false instruction bit.
FBtrueValue()1043 inline int FBtrueValue() const {
1044 return this->Bits(kFBtrueShift + kFBtrueBits - 1, kFBtrueShift);
1045 }
1046
1047 // Return the fields at their original place in the instruction encoding.
OpcodeFieldRaw()1048 inline Opcode OpcodeFieldRaw() const {
1049 return static_cast<Opcode>(this->InstructionBits() & kOpcodeMask);
1050 }
1051
RsFieldRaw()1052 inline int RsFieldRaw() const {
1053 DCHECK(this->InstructionType() == InstructionBase::kRegisterType ||
1054 this->InstructionType() == InstructionBase::kImmediateType);
1055 return this->InstructionBits() & kRsFieldMask;
1056 }
1057
RtFieldRaw()1058 inline int RtFieldRaw() const {
1059 DCHECK(this->InstructionType() == InstructionBase::kRegisterType ||
1060 this->InstructionType() == InstructionBase::kImmediateType);
1061 return this->InstructionBits() & kRtFieldMask;
1062 }
1063
RdFieldRaw()1064 inline int RdFieldRaw() const {
1065 DCHECK(this->InstructionType() == InstructionBase::kRegisterType);
1066 return this->InstructionBits() & kRdFieldMask;
1067 }
1068
SaFieldRaw()1069 inline int SaFieldRaw() const {
1070 return this->InstructionBits() & kSaFieldMask;
1071 }
1072
FunctionFieldRaw()1073 inline int FunctionFieldRaw() const {
1074 return this->InstructionBits() & kFunctionFieldMask;
1075 }
1076
1077 // Get the secondary field according to the opcode.
SecondaryValue()1078 inline int SecondaryValue() const {
1079 Opcode op = this->OpcodeFieldRaw();
1080 switch (op) {
1081 case SPECIAL:
1082 case SPECIAL2:
1083 return FunctionValue();
1084 case COP1:
1085 return RsValue();
1086 case REGIMM:
1087 return RtValue();
1088 default:
1089 return NULLSF;
1090 }
1091 }
1092
ImmValue(int bits)1093 inline int32_t ImmValue(int bits) const {
1094 DCHECK(this->InstructionType() == InstructionBase::kImmediateType);
1095 return this->Bits(bits - 1, 0);
1096 }
1097
Imm16Value()1098 inline int32_t Imm16Value() const {
1099 DCHECK(this->InstructionType() == InstructionBase::kImmediateType);
1100 return this->Bits(kImm16Shift + kImm16Bits - 1, kImm16Shift);
1101 }
1102
Imm18Value()1103 inline int32_t Imm18Value() const {
1104 DCHECK(this->InstructionType() == InstructionBase::kImmediateType);
1105 return this->Bits(kImm18Shift + kImm18Bits - 1, kImm18Shift);
1106 }
1107
Imm19Value()1108 inline int32_t Imm19Value() const {
1109 DCHECK(this->InstructionType() == InstructionBase::kImmediateType);
1110 return this->Bits(kImm19Shift + kImm19Bits - 1, kImm19Shift);
1111 }
1112
Imm21Value()1113 inline int32_t Imm21Value() const {
1114 DCHECK(this->InstructionType() == InstructionBase::kImmediateType);
1115 return this->Bits(kImm21Shift + kImm21Bits - 1, kImm21Shift);
1116 }
1117
Imm26Value()1118 inline int32_t Imm26Value() const {
1119 DCHECK((this->InstructionType() == InstructionBase::kJumpType) ||
1120 (this->InstructionType() == InstructionBase::kImmediateType));
1121 return this->Bits(kImm26Shift + kImm26Bits - 1, kImm26Shift);
1122 }
1123
1124 static bool IsForbiddenAfterBranchInstr(Instr instr);
1125
1126 // Say if the instruction should not be used in a branch delay slot or
1127 // immediately after a compact branch.
IsForbiddenAfterBranch()1128 inline bool IsForbiddenAfterBranch() const {
1129 return IsForbiddenAfterBranchInstr(this->InstructionBits());
1130 }
1131
IsForbiddenInBranchDelay()1132 inline bool IsForbiddenInBranchDelay() const {
1133 return IsForbiddenAfterBranch();
1134 }
1135
1136 // Say if the instruction 'links'. e.g. jal, bal.
1137 bool IsLinkingInstruction() const;
1138 // Say if the instruction is a break or a trap.
1139 bool IsTrap() const;
1140 };
1141
1142 class Instruction : public InstructionGetters<InstructionBase> {
1143 public:
1144 // Instructions are read of out a code stream. The only way to get a
1145 // reference to an instruction is to convert a pointer. There is no way
1146 // to allocate or create instances of class Instruction.
1147 // Use the At(pc) function to create references to Instruction.
At(byte * pc)1148 static Instruction* At(byte* pc) {
1149 return reinterpret_cast<Instruction*>(pc);
1150 }
1151
1152 private:
1153 // We need to prevent the creation of instances of class Instruction.
1154 DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction);
1155 };
1156
1157
1158 // -----------------------------------------------------------------------------
1159 // MIPS assembly various constants.
1160
1161 // C/C++ argument slots size.
1162 const int kCArgSlotCount = 4;
1163 const int kCArgsSlotsSize = kCArgSlotCount * Instruction::kInstrSize;
1164 const int kInvalidStackOffset = -1;
1165 // JS argument slots size.
1166 const int kJSArgsSlotsSize = 0 * Instruction::kInstrSize;
1167 // Assembly builtins argument slots size.
1168 const int kBArgsSlotsSize = 0 * Instruction::kInstrSize;
1169
1170 const int kBranchReturnOffset = 2 * Instruction::kInstrSize;
1171
InstructionType()1172 InstructionBase::Type InstructionBase::InstructionType() const {
1173 switch (OpcodeFieldRaw()) {
1174 case SPECIAL:
1175 if (FunctionFieldToBitNumber(FunctionFieldRaw()) &
1176 kFunctionFieldRegisterTypeMask) {
1177 return kRegisterType;
1178 }
1179 return kUnsupported;
1180 case SPECIAL2:
1181 switch (FunctionFieldRaw()) {
1182 case MUL:
1183 case CLZ:
1184 return kRegisterType;
1185 default:
1186 return kUnsupported;
1187 }
1188 break;
1189 case SPECIAL3:
1190 switch (FunctionFieldRaw()) {
1191 case INS:
1192 case EXT:
1193 return kRegisterType;
1194 case BSHFL: {
1195 int sa = SaFieldRaw() >> kSaShift;
1196 switch (sa) {
1197 case BITSWAP:
1198 case WSBH:
1199 case SEB:
1200 case SEH:
1201 return kRegisterType;
1202 }
1203 sa >>= kBp2Bits;
1204 switch (sa) {
1205 case ALIGN:
1206 return kRegisterType;
1207 default:
1208 return kUnsupported;
1209 }
1210 }
1211 default:
1212 return kUnsupported;
1213 }
1214 break;
1215 case COP1: // Coprocessor instructions.
1216 switch (RsFieldRawNoAssert()) {
1217 case BC1: // Branch on coprocessor condition.
1218 case BC1EQZ:
1219 case BC1NEZ:
1220 return kImmediateType;
1221 default:
1222 return kRegisterType;
1223 }
1224 break;
1225 case COP1X:
1226 return kRegisterType;
1227
1228 // 26 bits immediate type instructions. e.g.: j imm26.
1229 case J:
1230 case JAL:
1231 return kJumpType;
1232
1233 default:
1234 return kImmediateType;
1235 }
1236 }
1237
1238 #undef OpcodeToBitNumber
1239 #undef FunctionFieldToBitNumber
1240
1241 // -----------------------------------------------------------------------------
1242 // Instructions.
1243
1244 template <class P>
IsLinkingInstruction()1245 bool InstructionGetters<P>::IsLinkingInstruction() const {
1246 uint32_t op = this->OpcodeFieldRaw();
1247 switch (op) {
1248 case JAL:
1249 return true;
1250 case POP76:
1251 if (this->RsFieldRawNoAssert() == JIALC)
1252 return true; // JIALC
1253 else
1254 return false; // BNEZC
1255 case REGIMM:
1256 switch (this->RtFieldRaw()) {
1257 case BGEZAL:
1258 case BLTZAL:
1259 return true;
1260 default:
1261 return false;
1262 }
1263 case SPECIAL:
1264 switch (this->FunctionFieldRaw()) {
1265 case JALR:
1266 return true;
1267 default:
1268 return false;
1269 }
1270 default:
1271 return false;
1272 }
1273 }
1274
1275 template <class P>
IsTrap()1276 bool InstructionGetters<P>::IsTrap() const {
1277 if (this->OpcodeFieldRaw() != SPECIAL) {
1278 return false;
1279 } else {
1280 switch (this->FunctionFieldRaw()) {
1281 case BREAK:
1282 case TGE:
1283 case TGEU:
1284 case TLT:
1285 case TLTU:
1286 case TEQ:
1287 case TNE:
1288 return true;
1289 default:
1290 return false;
1291 }
1292 }
1293 }
1294
1295 // static
1296 template <class T>
IsForbiddenAfterBranchInstr(Instr instr)1297 bool InstructionGetters<T>::IsForbiddenAfterBranchInstr(Instr instr) {
1298 Opcode opcode = static_cast<Opcode>(instr & kOpcodeMask);
1299 switch (opcode) {
1300 case J:
1301 case JAL:
1302 case BEQ:
1303 case BNE:
1304 case BLEZ: // POP06 bgeuc/bleuc, blezalc, bgezalc
1305 case BGTZ: // POP07 bltuc/bgtuc, bgtzalc, bltzalc
1306 case BEQL:
1307 case BNEL:
1308 case BLEZL: // POP26 bgezc, blezc, bgec/blec
1309 case BGTZL: // POP27 bgtzc, bltzc, bltc/bgtc
1310 case BC:
1311 case BALC:
1312 case POP10: // beqzalc, bovc, beqc
1313 case POP30: // bnezalc, bnvc, bnec
1314 case POP66: // beqzc, jic
1315 case POP76: // bnezc, jialc
1316 return true;
1317 case REGIMM:
1318 switch (instr & kRtFieldMask) {
1319 case BLTZ:
1320 case BGEZ:
1321 case BLTZAL:
1322 case BGEZAL:
1323 return true;
1324 default:
1325 return false;
1326 }
1327 break;
1328 case SPECIAL:
1329 switch (instr & kFunctionFieldMask) {
1330 case JR:
1331 case JALR:
1332 return true;
1333 default:
1334 return false;
1335 }
1336 break;
1337 case COP1:
1338 switch (instr & kRsFieldMask) {
1339 case BC1:
1340 case BC1EQZ:
1341 case BC1NEZ:
1342 return true;
1343 break;
1344 default:
1345 return false;
1346 }
1347 break;
1348 default:
1349 return false;
1350 }
1351 }
1352 } // namespace internal
1353 } // namespace v8
1354
1355 #endif // #ifndef V8_MIPS_CONSTANTS_H_
1356