| /external/valgrind/none/tests/ppc64/ |
| D | round.c | 33 FMSUB, FNMADD, FNMSUB, FSQRT enumerator
926 for (s = (op != FSQRT ? -1 : 1); s < 2; s += 2) in check_double_guarded_arithmetic_op()
1034 case FSQRT: in check_double_guarded_arithmetic_op()
1139 case FSQRT: in check_double_guarded_arithmetic_op()
1208 for (op = FADD; op <= FSQRT; op++) { in test_float_arithmetic_ops()
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| /external/valgrind/none/tests/ppc32/ |
| D | round.c | 33 FMSUB, FNMADD, FNMSUB, FSQRT enumerator
926 for (s = (op != FSQRT ? -1 : 1); s < 2; s += 2) in check_double_guarded_arithmetic_op()
1034 case FSQRT: in check_double_guarded_arithmetic_op()
1139 case FSQRT: in check_double_guarded_arithmetic_op()
1208 for (op = FADD; op <= FSQRT; op++) { in test_float_arithmetic_ops()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 450 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 524 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
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| D | BasicTTIImpl.h | 201 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT); in haveFastSqrt()
742 ISDs.push_back(ISD::FSQRT); in getIntrinsicInstrCost()
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeInstrFPU.td | 110 def FSQRT : ArithF2<0x16, 0x380, "fsqrt ", IIC_FPUs>;
135 def : Pat<(fsqrt GPR:$V), (FSQRT GPR:$V)>;
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| D | MBlazeInstrFormats.td | 27 def FRRC : Format<10>; // SEXT8, SEXT16, SRA, SRC, SRL, FLT, FINT, FSQRT
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| /external/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 265 X86_INTRINSIC_DATA(avx_sqrt_pd_256, INTR_TYPE_1OP, ISD::FSQRT, 0),
266 X86_INTRINSIC_DATA(avx_sqrt_ps_256, INTR_TYPE_1OP, ISD::FSQRT, 0),
1429 X86_INTRINSIC_DATA(avx512_mask_sqrt_pd_128, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0),
1430 X86_INTRINSIC_DATA(avx512_mask_sqrt_pd_256, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0),
1431 X86_INTRINSIC_DATA(avx512_mask_sqrt_pd_512, INTR_TYPE_1OP_MASK_RM, ISD::FSQRT,
1433 X86_INTRINSIC_DATA(avx512_mask_sqrt_ps_128, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0),
1434 X86_INTRINSIC_DATA(avx512_mask_sqrt_ps_256, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0),
1435 X86_INTRINSIC_DATA(avx512_mask_sqrt_ps_512, INTR_TYPE_1OP_MASK_RM, ISD::FSQRT,
1873 X86_INTRINSIC_DATA(sse_sqrt_ps, INTR_TYPE_1OP, ISD::FSQRT, 0),
1923 X86_INTRINSIC_DATA(sse2_sqrt_pd, INTR_TYPE_1OP, ISD::FSQRT, 0),
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 301 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; in mightUseCTR()
344 Opcode = ISD::FSQRT; break; in mightUseCTR()
|
| D | PPCISelLowering.cpp | 192 setOperationAction(ISD::FSQRT, MVT::f64, Expand); in PPCTargetLowering()
197 setOperationAction(ISD::FSQRT, MVT::f32, Expand); in PPCTargetLowering()
463 setOperationAction(ISD::FSQRT, VT, Expand); in PPCTargetLowering()
534 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
590 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); in PPCTargetLowering()
817 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); in PPCTargetLowering()
820 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
823 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand); in PPCTargetLowering()
826 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand); in PPCTargetLowering()
884 setTargetDAGCombine(ISD::FSQRT); in PPCTargetLowering()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 174 case ISD::FSQRT: in LegalizeOp()
|
| D | LegalizeFloatTypes.cpp | 90 case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break; in SoftenFloatResult()
870 case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break; in ExpandFloatResult()
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| D | LegalizeVectorTypes.cpp | 87 case ISD::FSQRT: in ScalarizeVectorResult()
464 case ISD::FSQRT: in SplitVectorResult()
1311 case ISD::FSQRT: in WidenVectorResult()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaISelLowering.cpp | 120 setOperationAction(ISD::FSQRT, MVT::f64, Expand); in AlphaTargetLowering()
121 setOperationAction(ISD::FSQRT, MVT::f32, Expand); in AlphaTargetLowering()
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/ |
| D | MBlazeDisassembler.cpp | 235 case 0x380: return MBlaze::FSQRT; in decodeFADD()
|
| /external/v8/src/ppc/ |
| D | disasm-ppc.cc | 945 case FSQRT: { in DecodeExt4()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 158 case ISD::FSQRT: return "fsqrt"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 103 case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break; in SoftenFloatResult()
1040 case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break; in ExpandFloatResult()
1883 case ISD::FSQRT: in PromoteFloatResult()
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| D | LegalizeVectorOps.cpp | 308 case ISD::FSQRT: in LegalizeOp()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 547 // FDIV,FSQRT
549 // TODO: Specialize FSQRT for longer latency.
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 157 defm FSQRT : FFR1P_M<0x4, "sqrt", fsqrt>;
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 1071 FSQRT = FSQRT_s, enumerator
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| D | disasm-arm64.cc | 1001 FORMAT(FSQRT, "fsqrt"); in VisitFPDataProcessing1Source()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1747 setOperationAction(ISD::FSQRT, MVT::f128, Legal); in SparcTargetLowering()
1772 setOperationAction(ISD::FSQRT, MVT::f128, Custom); in SparcTargetLowering()
1824 setOperationAction(ISD::FSQRT, MVT::f32, Promote); in SparcTargetLowering()
3071 case ISD::FSQRT: return LowerF128Op(Op, DAG, in LowerOperation()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 356 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
|