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Searched refs:LogicVRegister (Results 1 – 4 of 4) sorted by relevance

/external/vixl/src/aarch64/
Dsimulator-aarch64.h360 class LogicVRegister {
362 inline LogicVRegister( in LogicVRegister() function
579 LogicVRegister& SignedSaturate(VectorFormat vform) { in SignedSaturate()
591 LogicVRegister& UnsignedSaturate(VectorFormat vform) { in UnsignedSaturate()
610 LogicVRegister& Round(VectorFormat vform) { in Round()
619 LogicVRegister& Uhalve(VectorFormat vform) { in Uhalve()
635 LogicVRegister& Halve(VectorFormat vform) { in Halve()
1843 void ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr);
1844 void ld1(VectorFormat vform, LogicVRegister dst, int index, uint64_t addr);
1845 void ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr);
[all …]
Dlogic-aarch64.cc402 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1()
412 LogicVRegister dst, in ld1()
419 void Simulator::ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1r()
428 LogicVRegister dst1, in ld2()
429 LogicVRegister dst2, in ld2()
445 LogicVRegister dst1, in ld2()
446 LogicVRegister dst2, in ld2()
458 LogicVRegister dst1, in ld2r()
459 LogicVRegister dst2, in ld2r()
472 LogicVRegister dst1, in ld3()
[all …]
Dsimulator-aarch64.cc2382 LogicVRegister(ReadVRegister(dst)) in VisitFPIntegerConvert()
2386 WriteXRegister(dst, LogicVRegister(ReadVRegister(src)).Uint(kFormatD, 1)); in VisitFPIntegerConvert()
3887 uint64_t value = LogicVRegister(rn).Uint(vf, reg_index); in VisitNEONCopy()
3891 int64_t value = LogicVRegister(rn).Int(vf, reg_index); in VisitNEONCopy()
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc2838 LogicVRegister reg(simulator.ReadVRegister(i)); in TraceTestHelper()