| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelDAGToDAG.cpp | 254 SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32, in Select()
290 unsigned Opc = (Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64); in Select()
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| D | MipsInstrInfo.cpp | 118 Opc = Mips::MFLO, SrcReg = 0; in copyPhysReg()
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| D | MipsInstrInfo.td | 759 def MFLO : MoveFromLOHI<0x12, "mflo">;
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_64.c | 398 return push_inst(compiler, MFLO | D(dst), DR(dst)); in emit_single_op()
401 return push_inst(compiler, MFLO | D(dst), DR(dst)); in emit_single_op()
406 FAIL_IF(push_inst(compiler, MFLO | D(dst), DR(dst))); in emit_single_op()
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| D | sljitNativeMIPS_32.c | 306 return push_inst(compiler, MFLO | D(dst), DR(dst)); in emit_single_op()
311 FAIL_IF(push_inst(compiler, MFLO | D(dst), DR(dst))); in emit_single_op()
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| D | sljitNativeMIPS_common.c | 149 #define MFLO (HI(0) | LO(18)) macro
1054 FAIL_IF(push_inst(compiler, MFLO | D(SLJIT_R0), DR(SLJIT_R0))); in sljit_emit_op0()
1075 FAIL_IF(push_inst(compiler, MFLO | D(SLJIT_R0), DR(SLJIT_R0))); in sljit_emit_op0()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 100 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; in copyPhysReg()
238 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0); in storeRegToStack()
350 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; in expandPostRAPseudo()
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| D | MipsISelLowering.h | 78 MFLO, enumerator
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| D | MipsSEISelLowering.cpp | 445 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); in selectMADD()
517 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub); in selectMSUB()
1284 Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult); in lowerMulDiv()
1304 SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op); in extractLOHI()
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| D | MipsSEFrameLowering.cpp | 800 Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO; in spillCalleeSavedRegisters()
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| D | MipsFastISel.cpp | 1698 : Mips::MFLO; in selectDivRem()
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| D | MipsInstrInfo.td | 92 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
1977 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
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| D | Mips16InstrInfo.td | 883 // Format: MFLO rx MIPS16e
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| D | MipsISelLowering.cpp | 128 case MipsISD::MFLO: return "MipsISD::MFLO"; in getTargetNodeName()
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| /external/v8/src/mips/ |
| D | constants-mips.h | 430 MFLO = ((2U << 3) + 2), enumerator
931 FunctionFieldToBitNumber(MFHI) | FunctionFieldToBitNumber(MFLO) |
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| D | disasm-mips.cc | 1106 case MFLO: in DecodeTypeRegisterSPECIAL()
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| D | assembler-mips.cc | 2096 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFLO); in mflo()
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| D | simulator-mips.cc | 3757 case MFLO: in DecodeTypeRegisterSPECIAL()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 413 MFLO = ((2U << 3) + 2), enumerator
972 FunctionFieldToBitNumber(MFHI) | FunctionFieldToBitNumber(MFLO) |
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| D | disasm-mips64.cc | 1257 case MFLO: in DecodeTypeRegisterSPECIAL()
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| D | assembler-mips64.cc | 2348 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFLO); in mflo()
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| D | simulator-mips64.cc | 3708 case MFLO: // MFLO == DCLZ on R6. in DecodeTypeRegisterSPECIAL()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3098 TOut.emitR(Mips::MFLO, RdReg, IDLoc, STI); in expandDiv()
3126 TOut.emitR(Mips::MFLO, RdReg, IDLoc, STI); in expandDiv()
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| /external/valgrind/none/tests/mips32/ |
| D | MIPS32int.stdout.exp-mips32-LE | 1090 MFHI MFLO
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| D | MIPS32int.stdout.exp-mips32-BE | 1090 MFHI MFLO
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