| /external/vixl/test/aarch32/config/ |
| D | cond-rd-operand-rn-shift-rs-t32.json | 41 "Movs" // MOVS{<q>} <Rdm>, <Rdm>, ASR <Rs> ; T1
42 // MOVS{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1
43 // MOVS{<q>} <Rdm>, <Rdm>, LSR <Rs> ; T1
44 // MOVS{<q>} <Rdm>, <Rdm>, ROR <Rs> ; T1
45 // MOVS{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; T2
113 "Movs" // MOVS{<q>} <Rdm>, <Rdm>, ASR <Rs> ; T1
114 // MOVS{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1
115 // MOVS{<q>} <Rdm>, <Rdm>, LSR <Rs> ; T1
116 // MOVS{<q>} <Rdm>, <Rdm>, ROR <Rs> ; T1
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| D | cond-rd-operand-rn-shift-amount-1to32-t32.json | 29 // MNEMONIC{<c>}.N <Rn>, <Rm>, LSL|ROR #<amount> ; Special case for MOV and MOVS
37 "Movs", // MOVS{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2
38 // MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T3
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| D | cond-rd-operand-const-a32.json | 32 "Movs", // MOVS{<c>}{<q>} <Rd>, #<const> ; A1
76 "Movs", // MOVS{<c>}{<q>} <Rd>, #<const> ; A1
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| D | cond-rd-operand-rn-shift-amount-1to31-t32.json | 36 "Movs", // MOVS{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2
37 // MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T3
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| D | cond-rd-operand-rn-t32.json | 45 "Movs", // MOVS{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2
46 // MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T3
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| D | cond-rdlow-operand-imm8-t32.json | 34 "Movs" // MOVS{<q>} <Rd>, #<imm8> ; T1
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| D | cond-rd-operand-const-t32.json | 35 "Movs", // MOVS{<c>}{<q>} <Rd>, #<const> ; T2
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| D | cond-rd-operand-rn-shift-rs-a32.json | 32 "Movs", // MOVS{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; A1
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| D | cond-rd-operand-rn-shift-amount-1to31-a32.json | 32 "Movs", // MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1
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| D | cond-rd-operand-rn-shift-amount-1to32-a32.json | 32 "Movs", // MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1
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| D | cond-rd-operand-rn-a32.json | 40 "Movs", // MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1
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| /external/tremolo/Tremolo/ |
| D | dpen.s | 99 MOVS r0, r0, LSR #1 @ r0 = lok>>1 C = bottom bit
124 MOVS r0, r0, LSR #1 @ r0 = lok>>1 C = bottom bit
156 MOVS r0, r0, LSR #1 @ r0 = lok>>1 C = bottom bit
181 MOVS r0, r0, LSR #1 @ r0 = lok>>1 C = bottom bit
214 MOVS r0, r0, LSR #1 @ r0 = lok>>1 C = bottom bit
464 MOVS r12,r0
474 MOVS r6,r3 @ r6 = j = post
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| D | floor1ARM.s | 59 MOVS r6, r6, LSR #15
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| /external/aac/libSBRdec/src/arm/ |
| D | env_calc_arm.cpp | 118 MOVS r3, r3, ASR #1 in FDK_get_maxval()
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_T2_32.c | 126 #define MOVS 0x0000 macro
645 return push_inst16(compiler, MOVS | RD3(dst) | RN3(reg)); in emit_op_imm()
2017 return push_inst16(compiler, MOVS | RD3(TMP_REG1) | RN3(dst)); in sljit_emit_op_flags()
2051 return push_inst16(compiler, MOVS | RD3(TMP_REG1) | RN3(dst_r)); in sljit_emit_op_flags()
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| /external/llvm/lib/Target/X86/ |
| D | X86SchedHaswell.td | 986 // MOVS.
992 def : InstRW<[WriteMOVS], (instregex "MOVS(B|L|Q|W)")>;
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| D | X86InstrInfo.td | 1964 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
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| D | X86InstrAVX512.td | 3063 // MOVS{S,D} to the lower bits.
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| D | X86InstrSSE.td | 7108 // MOVS{S,D} to the lower bits.
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrInfo.td | 1239 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
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| D | X86InstrSSE.td | 545 // MOVS{S,D} to the lower bits.
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| /external/llvm/test/MC/ARM/ |
| D | v8_IT_manual.s | 101 @ MOV reg, encoding T3 (32-bit) -- can only appear as MOVS or MOV.W
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