1// Copyright 2016, VIXL authors 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are met: 6// 7// * Redistributions of source code must retain the above copyright notice, 8// this list of conditions and the following disclaimer. 9// * Redistributions in binary form must reproduce the above copyright notice, 10// this list of conditions and the following disclaimer in the documentation 11// and/or other materials provided with the distribution. 12// * Neither the name of ARM Limited nor the names of its contributors may be 13// used to endorse or promote products derived from this software without 14// specific prior written permission. 15// 16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27{ 28 "mnemonics": [ 29 "Cmn", // CMN{<c>}{<q>} <Rn>, <Rm>, <shift> <Rs> ; A1 30 "Cmp", // CMP{<c>}{<q>} <Rn>, <Rm>, <shift> <Rs> ; A1 31 "Mov", // MOV{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; A1 32 "Movs", // MOVS{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; A1 33 "Mvn", // MVN{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; A1 34 "Mvns", // MVNS{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; A1 35 "Teq", // TEQ{<c>}{<q>} <Rn>, <Rm>, <shift> <Rs> ; A1 36 "Tst" // TST{<c>}{<q>} <Rn>, <Rm>, <shift> <Rs> ; A1 37 ], 38 "description" : { 39 "operands": [ 40 { 41 "name": "cond", 42 "type": "Condition" 43 }, 44 { 45 "name": "rd", 46 "type": "AllRegistersButPC" 47 }, 48 { 49 "name": "op", 50 "wrapper": "Operand", 51 "operands": [ 52 { 53 "name": "rn", 54 "type": "AllRegistersButPC" 55 }, 56 { 57 "name": "shift", 58 "type": "Shift" 59 }, 60 { 61 "name": "rs", 62 "type": "AllRegistersButPC" 63 } 64 ] 65 } 66 ], 67 "inputs": [ 68 { 69 "name": "apsr", 70 "type": "NZCV" 71 }, 72 { 73 "name": "rd", 74 "type": "Register" 75 }, 76 { 77 "name": "rn", 78 "type": "Register" 79 }, 80 { 81 "name": "rs", 82 "type": "RegisterShift" 83 } 84 ] 85 }, 86 "test-files": [ 87 { 88 "type": "assembler", 89 "test-cases": [ 90 { 91 "name": "Operands", 92 "operands": [ 93 "cond", "rd", "rn", "shift", "rs" 94 ], 95 "operand-limit": 1000 96 } 97 ] 98 }, 99 { 100 "type": "simulator", 101 "test-cases": [ 102 { 103 "name": "Condition", 104 "operands": [ 105 "cond" 106 ], 107 "inputs": [ 108 "apsr" 109 ] 110 }, 111 // Test combinations of registers values with rd == rn. 112 { 113 "name": "RdIsRn", 114 "operands": [ 115 "rd", "rn" 116 ], 117 "inputs": [ 118 "rd", "rn" 119 ], 120 "operand-filter": "rd == rn", 121 "input-filter": "rd == rn" 122 }, 123 // Test combinations of registers values with rd != rn. 124 { 125 "name": "RdIsNotRn", 126 "operands": [ 127 "rd", "rn" 128 ], 129 "inputs": [ 130 "rd", "rn" 131 ], 132 "operand-filter": "rd != rn", 133 "operand-limit": 10, 134 "input-limit": 200 135 }, 136 // Test combinations of shift types and register values. 137 { 138 "name": "ShiftTypes", 139 "operands": [ 140 "rn", "shift", "rs" 141 ], 142 "inputs": [ 143 "rn", "rs" 144 ], 145 // Make sure the registers are different. 146 "operand-filter": "rn == 'r1' and rs == 'r2'" 147 } 148 ] 149 } 150 ] 151} 152