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/external/swiftshader/third_party/LLVM/test/CodeGen/MBlaze/
Dmul.ll6 ; RUN: llc < %s -march=mblaze -mattr=+mul | FileCheck -check-prefix=MUL %s
10 ; MUL: test_i8:
15 ; MUL-NOT: brlid
19 ; MUL: rtsd
20 ; MUL: mul
25 ; MUL: test_i16:
30 ; MUL-NOT: brlid
34 ; MUL: rtsd
35 ; MUL: mul
40 ; MUL: test_i32:
[all …]
Dmul64.ll7 ; RUN: FileCheck -check-prefix=MUL %s
11 ; MUL: test_i64:
16 ; MUL-NOT: brlid
17 ; MUL: mulh
18 ; MUL: mul
22 ; MUL: rtsd
/external/llvm/test/Transforms/InstCombine/
Doverflow-mul.ll11 ; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
13 ; CHECK: extractvalue { i32, i1 } [[MUL]], 1
26 ; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
28 ; CHECK: extractvalue { i32, i1 } [[MUL]], 1
42 ; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
44 ; CHECK-DAG: [[VAL:%.*]] = extractvalue { i32, i1 } [[MUL]], 0
46 ; CHECK-DAG: [[OVFL:%.*]] = extractvalue { i32, i1 } [[MUL]], 1
74 ; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
76 ; CHECK: extractvalue { i32, i1 } [[MUL]], 1
90 ; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y)
[all …]
/external/llvm/test/CodeGen/NVPTX/
Dfma-disable.ll2 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 -nvptx-fma-level=0 | FileCheck %s -check-prefix=MUL
4 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -nvptx-fma-level=0 | FileCheck %s -check-prefix=MUL
9 ; MUL: mul.rn.f32
10 ; MUL: add.rn.f32
19 ; MUL: mul.rn.f64
20 ; MUL: add.rn.f64
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.pow.ll5 ;CHECK-NEXT: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
19 ;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
21 ;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
25 ;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
27 ;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
Dfsqrt.ll31 ; R600: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[2].Z, PS
44 ; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[2].W, PS
46 ; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].X, PS
61 ; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].Y, PS
63 ; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].Z, PS
65 ; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].W, PS
67 ; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[4].X, PS
Dmul_uint24.ll26 ; SI: v_mul_u32_u24_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
27 ; SI: v_bfe_i32 v{{[0-9]}}, [[MUL]], 0, 16
40 ; SI: v_mul_u32_u24_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
41 ; SI: v_bfe_i32 v{{[0-9]}}, [[MUL]], 0, 8
Dfp_to_sint.f64.ll40 ; CI-DAG: v_mul_f64 [[MUL:v\[[0-9]+:[0-9]+\]]], [[VAL]], s{{\[}}[[K0_LO]]:[[K0_HI]]{{\]}}
41 ; CI-DAG: v_floor_f64_e32 [[FLOOR:v\[[0-9]+:[0-9]+\]]], [[MUL]]
Dfdiv.f64.ll26 ; COMMON-DAG: v_mul_f64 [[MUL:v\[[0-9]+:[0-9]+\]]], [[SCALE1]], [[FMA3]]
27 ; COMMON-DAG: v_fma_f64 [[FMA4:v\[[0-9]+:[0-9]+\]]], -[[SCALE0]], [[MUL]], [[SCALE1]]
28 ; COMMON: v_div_fmas_f64 [[FMAS:v\[[0-9]+:[0-9]+\]]], [[FMA4]], [[FMA3]], [[MUL]]
/external/mesa3d/src/gallium/drivers/r300/compiler/tests/
Dregalloc_tex_1d_swizzle.test8 6: MUL temp[17].xyz, temp[8].xyz_, input[0].xyz_;
13 11: MUL temp[21].xyz, temp[17].xyz_, temp[18].xxx_;
14 12: MUL output[0].xyz, temp[21].xyz_, temp[20].www_;
/external/tremolo/Tremolo/
DmdctLARM.s202 MUL r11,r12,r11 @ r11 = *l * *wL++
242 MUL r11,r12,r11 @ (r14,r11) = *l * *wL++
244 MUL r6, r7, r6 @ (r14,r6) = *--r * *--wR
327 MUL r9, r6, r10 @ r9 = s0*T[0]
331 MUL r12,r7, r10 @ r12 = s2*T[0]
347 MUL r9, r6, r10 @ r9 = s0*T[1]
351 MUL r12,r7, r10 @ r12 = s2*T[1]
379 MUL r12,r8, r11 @ r12 = ro0*T[1]
383 MUL r3, r9, r11 @ r3 = ro2*T[1]
392 MUL r12,r6, r10 @ r12 = ri0*T[0]
[all …]
/external/v8/src/ic/
Dic-state.cc152 GENERATE(Token::MUL, INT32, INT32, INT32); in GenerateAheadOfTime()
153 GENERATE(Token::MUL, INT32, INT32, NUMBER); in GenerateAheadOfTime()
154 GENERATE(Token::MUL, INT32, NUMBER, NUMBER); in GenerateAheadOfTime()
155 GENERATE(Token::MUL, INT32, SMI, INT32); in GenerateAheadOfTime()
156 GENERATE(Token::MUL, INT32, SMI, NUMBER); in GenerateAheadOfTime()
157 GENERATE(Token::MUL, NUMBER, INT32, NUMBER); in GenerateAheadOfTime()
158 GENERATE(Token::MUL, NUMBER, NUMBER, NUMBER); in GenerateAheadOfTime()
159 GENERATE(Token::MUL, NUMBER, SMI, NUMBER); in GenerateAheadOfTime()
160 GENERATE(Token::MUL, SMI, INT32, INT32); in GenerateAheadOfTime()
161 GENERATE(Token::MUL, SMI, INT32, NUMBER); in GenerateAheadOfTime()
[all …]
/external/mesa3d/src/gallium/tests/graw/fragment-shader/
Dfrag-flr.sh11 MUL TEMP[0], IN[0], IMM[0]
13 MUL OUT[0], TEMP[0], IMM[1]
Dfrag-mul.sh8 MUL OUT[0], IN[0], IMM[0]
Dfrag-ex2.sh9 MUL OUT[0], TEMP[0], IN[0]
Dfrag-frc.sh10 MUL TEMP[0], IN[0], IMM[0]
/external/mesa3d/src/gallium/tests/graw/vertex-shader/
Dvert-ex2.sh14 MUL TEMP[0], TEMP[0], IMM[0]
16 MUL OUT[1], TEMP[0], TEMP[1]
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp3288 MachineInstr *MUL = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg()); in genFusedMultiply() local
3290 unsigned SrcReg0 = MUL->getOperand(1).getReg(); in genFusedMultiply()
3291 bool Src0IsKill = MUL->getOperand(1).isKill(); in genFusedMultiply()
3292 unsigned SrcReg1 = MUL->getOperand(2).getReg(); in genFusedMultiply()
3293 bool Src1IsKill = MUL->getOperand(2).isKill(); in genFusedMultiply()
3317 .addImm(MUL->getOperand(3).getImm()); in genFusedMultiply()
3327 return MUL; in genFusedMultiply()
3352 MachineInstr *MUL = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg()); in genMaddR() local
3354 unsigned SrcReg0 = MUL->getOperand(1).getReg(); in genMaddR()
3355 bool Src0IsKill = MUL->getOperand(1).isKill(); in genMaddR()
[all …]
/external/toybox/toys/pending/
Dexpr.c132 enum { OR = 1, AND, EQ, NE, GT, GTE, LT, LTE, ADD, SUB, MUL, DIVI, MOD, RE }; enumerator
148 {"*", 5, I_TO_I, MUL }, {"/", 5, I_TO_I, DIVI }, {"%", 5, I_TO_I, MOD },
194 case MUL: x = a * b; break; in eval_op()
/external/mesa3d/src/mesa/drivers/dri/i965/
Dtest_vec4_register_coalesce.cpp138 vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f))); in TEST_F()
162 vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f))); in TEST_F()
229 vec4_instruction *mul = v->emit(v->MUL(temp, some_src_1, some_src_2)); in TEST_F()
/external/webp/src/dsp/
Denc.c108 #define MUL(a, b) (((a) * (b)) >> 16) macro
118 const int c = MUL(in[4], kC2) - MUL(in[12], kC1); in ITransformOne()
119 const int d = MUL(in[4], kC1) + MUL(in[12], kC2); in ITransformOne()
133 const int c = MUL(tmp[4], kC2) - MUL(tmp[12], kC1); in ITransformOne()
134 const int d = MUL(tmp[4], kC1) + MUL(tmp[12], kC2); in ITransformOne()
215 #undef MUL
/external/llvm/test/Transforms/SafeStack/
Dsetjmp2.ll20 ; CHECK-NEXT: %[[MUL:.*]] = mul i64 %[[ZEXT]], 4
23 ; CHECK-NEXT: %[[SUB:.*]] = sub i64 %[[PTRTOINT]], %[[MUL]]
/external/llvm/test/CodeGen/X86/
Dcombine-multiplies.ll33 ; CHECK: imull $400, [[ARG1:%[a-z]+]], [[MUL:%[a-z]+]] # imm = 0x190
34 ; CHECK-NEXT: leal ([[ARG2:%[a-z]+]],[[MUL]]), [[LEA:%[a-z]+]]
36 ; CHECK-NEXT: movl $22, {{[0-9]+}}([[ARG2]],[[MUL]])
37 ; CHECK-NEXT: movl $33, {{[0-9]+}}([[ARG2]],[[MUL]])
/external/vixl/test/aarch32/config/
Dcond-rdlow-rnlow-rmlow-t32.json32 "Mul", // MUL<c>{<q>} <Rdm>, <Rn>, {<Rdm>} ; T1
93 "Mul" // MUL<c>{<q>} <Rdm>, <Rn>, {<Rdm>} ; T1
/external/antlr/antlr-3.4/runtime/Python/tests/
Dt048rewrite2.g10 MUL : '*';

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