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Searched refs:NumMicroOps (Results 1 – 21 of 21) sorted by relevance

/external/llvm/lib/Target/AArch64/
DAArch64SchedA57WriteRes.td59 let NumMicroOps = 2;
65 let NumMicroOps = 2;
70 let NumMicroOps = 2;
75 let NumMicroOps = 2;
79 let NumMicroOps = 2;
83 let NumMicroOps = 2;
87 let NumMicroOps = 2;
91 let NumMicroOps = 2;
95 let NumMicroOps = 2;
100 let NumMicroOps = 2;
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DAArch64SchedKryoDetails.td17 let Latency = 3; let NumMicroOps = 2;
24 let Latency = 3; let NumMicroOps = 2;
31 let Latency = 4; let NumMicroOps = 3;
37 let Latency = 4; let NumMicroOps = 4;
43 let Latency = 3; let NumMicroOps = 4;
49 let Latency = 3; let NumMicroOps = 2;
55 let Latency = 3; let NumMicroOps = 2;
61 let Latency = 3; let NumMicroOps = 2;
67 let Latency = 3; let NumMicroOps = 2;
73 let Latency = 3; let NumMicroOps = 2;
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DAArch64SchedKryo.td63 { let Latency = 2; let NumMicroOps = 2; }
65 { let Latency = 2; let NumMicroOps = 2; }
67 { let Latency = 2; let NumMicroOps = 2; }
70 { let Latency = 8; let NumMicroOps = 1; } // Fragent -1
72 { let Latency = 8; let NumMicroOps = 1; } // Fragent -1
84 { let Latency = 3; let NumMicroOps = 2; }
90 { let Latency = 6; let NumMicroOps = 2; }
92 { let Latency = 12; let NumMicroOps = 2; } // Fragent -1 / NoRSV +1
DAArch64SchedVulcan.td149 let NumMicroOps = 2;
156 let NumMicroOps = 3;
162 let NumMicroOps = 2;
168 let NumMicroOps = 2;
174 let NumMicroOps = 2;
180 let NumMicroOps = 2;
186 let NumMicroOps = 2;
355 let NumMicroOps = 2;
372 let NumMicroOps = 3;
379 let NumMicroOps = 2;
DAArch64SchedCyclone.td177 let NumMicroOps = 2;
/external/llvm/lib/Target/X86/
DX86SchedHaswell.td279 let NumMicroOps = 2;
285 let NumMicroOps = 3;
292 let NumMicroOps = 2;
295 let NumMicroOps = 3;
301 let NumMicroOps = 2;
307 let NumMicroOps = 2;
313 let NumMicroOps = 3;
318 let NumMicroOps = 2;
322 let NumMicroOps = 3;
336 let NumMicroOps = 5;
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/external/llvm/include/llvm/MC/
DMCSchedule.h108 unsigned short NumMicroOps; member
119 return NumMicroOps != InvalidNumMicroOps; in isValid()
122 return NumMicroOps == VariantNumMicroOps; in isVariant()
DMCInstrItineraries.h98 int NumMicroOps; ///< # of micro-ops, -1 means it's variable member
233 return Itineraries[ItinClassIndx].NumMicroOps; in getNumMicroOps()
/external/llvm/lib/Target/ARM/
DARMScheduleSwift.td84 let NumMicroOps = 2;
88 let NumMicroOps = 3;
259 let NumMicroOps = 3;
264 let NumMicroOps = 0;
268 let NumMicroOps = 0;
272 let NumMicroOps = 0;
281 let NumMicroOps = 5;
298 let NumMicroOps = 1;
311 let NumMicroOps = 2;
315 let NumMicroOps = 2;
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DARMScheduleA9.td1925 // other writes associated with the operand have NumMicroOps = 0.
1943 let NumMicroOps = 0; }
1946 let NumMicroOps = 0; }
1991 def A9WriteAdr : SchedWriteRes<[A9UnitAGU]> { let NumMicroOps = 0; }
1997 let NumMicroOps = 0; }
2014 def A9WriteCycle1 : SchedWriteRes<[]> { let Latency = 1; let NumMicroOps = 0; }
2054 let NumMicroOps = 0; }
2058 let NumMicroOps = 0; }
2116 let NumMicroOps = 0;
2528 def : WriteRes<WriteNoop, []> { let Latency = 0; let NumMicroOps = 0; }
DARMSchedule.td50 // NumMicroOps = 2; // Dispatch 2 micro-ops.
/external/swiftshader/third_party/LLVM/include/llvm/MC/
DMCInstrItineraries.h98 unsigned NumMicroOps; ///< # of micro-ops, 0 means it's variable member
246 return Itineraries[ItinClassIndx].NumMicroOps != 1; in isMicroCoded()
/external/llvm/utils/TableGen/
DSubtargetEmitter.cpp573 Intinerary.NumMicroOps << ", " << in EmitItineraries()
814 SCDesc.NumMicroOps = 0; in GenSchedClassTables()
838 SCDesc.NumMicroOps = MCSchedClassDesc::VariantNumMicroOps; in GenSchedClassTables()
918 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps; in GenSchedClassTables()
922 SCDesc.NumMicroOps += WriteRes->getValueAsInt("NumMicroOps"); in GenSchedClassTables()
968 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps; in GenSchedClassTables()
989 if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) { in GenSchedClassTables()
1132 OS << MCDesc.NumMicroOps in EmitSchedClassTables()
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetSchedule.td76 // NumMicroOps represents the number of micro-operations that each instruction
82 int NumMicroOps = ops;
/external/swiftshader/third_party/LLVM/lib/Target/
DTargetInstrInfo.cpp55 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; in getNumMicroOps()
/external/llvm/include/llvm/Target/
DTargetItinerary.td86 // NumMicroOps represents the number of micro-operations that each instruction
114 int NumMicroOps = uops;
DTargetSchedule.td159 // and moving them into a reservation station.) Normally NumMicroOps
252 int NumMicroOps = 1;
288 // should either override the write's NumMicroOps to be greater than 1
/external/llvm/lib/CodeGen/
DTargetSchedule.cpp86 return SC->NumMicroOps; in getNumMicroOps()
DTargetInstrInfo.cpp1018 int UOps = ItinData->Itineraries[Class].NumMicroOps; in getNumMicroOps()
/external/swiftshader/third_party/LLVM/utils/TableGen/
DSubtargetEmitter.cpp505 Intinerary.NumMicroOps << ", " << in EmitProcessorData()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMBaseInstrInfo.cpp1983 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; in getNumMicroOps()
2681 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; in getInstrLatency()