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Searched refs:OUT_BATCH (Results 1 – 25 of 83) sorted by relevance

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/external/mesa3d/src/mesa/drivers/dri/i965/
Dgen6_gs_state.c74 OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2)); in upload_gs_state_for_tf()
75 OUT_BATCH(brw->ff_gs.prog_offset); in upload_gs_state_for_tf()
76 OUT_BATCH(GEN6_GS_SPF_MODE | GEN6_GS_VECTOR_MASK_ENABLE); in upload_gs_state_for_tf()
77 OUT_BATCH(0); /* no scratch space */ in upload_gs_state_for_tf()
78 OUT_BATCH((2 << GEN6_GS_DISPATCH_START_GRF_SHIFT) | in upload_gs_state_for_tf()
80 OUT_BATCH(((devinfo->max_gs_threads - 1) << GEN6_GS_MAX_THREADS_SHIFT) | in upload_gs_state_for_tf()
84 OUT_BATCH(GEN6_GS_SVBI_PAYLOAD_ENABLE | in upload_gs_state_for_tf()
107 OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (5 - 2)); in upload_gs_state()
108 OUT_BATCH(0); in upload_gs_state()
109 OUT_BATCH(0); in upload_gs_state()
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Dgen8_ds_state.c47 OUT_BATCH(_3DSTATE_DS << 16 | (ds_pkt_len - 2)); in gen8_upload_ds_state()
48 OUT_BATCH(stage_state->prog_offset); in gen8_upload_ds_state()
49 OUT_BATCH(0); in gen8_upload_ds_state()
50 OUT_BATCH(SET_FIELD(DIV_ROUND_UP(stage_state->sampler_count, 4), in gen8_upload_ds_state()
59 OUT_BATCH(0); in gen8_upload_ds_state()
60 OUT_BATCH(0); in gen8_upload_ds_state()
62 OUT_BATCH(SET_FIELD(prog_data->dispatch_grf_start_reg, in gen8_upload_ds_state()
67 OUT_BATCH(GEN7_DS_ENABLE | in gen8_upload_ds_state()
74 OUT_BATCH(SET_FIELD(vue_prog_data->cull_distance_mask, in gen8_upload_ds_state()
79 OUT_BATCH(0); in gen8_upload_ds_state()
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Dgen6_constant_state.c42 OUT_BATCH(opcode << 16 | (dwords - 2)); in gen7_upload_constant_state()
56 OUT_BATCH(0); in gen7_upload_constant_state()
57 OUT_BATCH(stage_state->push_const_size); in gen7_upload_constant_state()
59 OUT_BATCH(active ? stage_state->push_const_size : 0); in gen7_upload_constant_state()
60 OUT_BATCH(0); in gen7_upload_constant_state()
66 OUT_BATCH(0); in gen7_upload_constant_state()
67 OUT_BATCH(0); in gen7_upload_constant_state()
68 OUT_BATCH(0); in gen7_upload_constant_state()
69 OUT_BATCH(0); in gen7_upload_constant_state()
75 OUT_BATCH(0); in gen7_upload_constant_state()
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Dbrw_pipe_control.c132 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2)); in brw_emit_pipe_control_flush()
133 OUT_BATCH(flags); in brw_emit_pipe_control_flush()
134 OUT_BATCH(0); in brw_emit_pipe_control_flush()
135 OUT_BATCH(0); in brw_emit_pipe_control_flush()
136 OUT_BATCH(0); in brw_emit_pipe_control_flush()
137 OUT_BATCH(0); in brw_emit_pipe_control_flush()
154 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2)); in brw_emit_pipe_control_flush()
155 OUT_BATCH(flags); in brw_emit_pipe_control_flush()
156 OUT_BATCH(0); in brw_emit_pipe_control_flush()
157 OUT_BATCH(0); in brw_emit_pipe_control_flush()
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Dbrw_misc_state.c56 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2)); in upload_drawing_rect()
57 OUT_BATCH(0); /* xmin, ymin */ in upload_drawing_rect()
58 OUT_BATCH(((fb_width - 1) & 0xffff) | ((fb_height - 1) << 16)); in upload_drawing_rect()
59 OUT_BATCH(0); in upload_drawing_rect()
84 OUT_BATCH(MI_FLUSH); in upload_pipelined_state_pointers()
89 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2)); in upload_pipelined_state_pointers()
96 OUT_BATCH(0); in upload_pipelined_state_pointers()
604 OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2)); in brw_emit_depth_stencil_hiz()
605 OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) | in brw_emit_depth_stencil_hiz()
619 OUT_BATCH(0); in brw_emit_depth_stencil_hiz()
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Dgen8_depth_state.c64 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (8 - 2)); in emit_depth_packets()
65 OUT_BATCH(depth_surface_type << 29 | in emit_depth_packets()
75 OUT_BATCH(0); in emit_depth_packets()
76 OUT_BATCH(0); in emit_depth_packets()
78 OUT_BATCH(((width - 1) << 4) | ((height - 1) << 18) | lod); in emit_depth_packets()
79 OUT_BATCH(((depth - 1) << 21) | (min_array_element << 10) | mocs_wb); in emit_depth_packets()
80 OUT_BATCH(0); in emit_depth_packets()
81 OUT_BATCH(((depth - 1) << 21) | (depth_mt ? depth_mt->qpitch >> 2 : 0)); in emit_depth_packets()
86 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2)); in emit_depth_packets()
87 OUT_BATCH(0); in emit_depth_packets()
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Dhsw_sol.c108 OUT_BATCH(HSW_MI_MATH | (9 - 2)); in tally_prims_written()
110 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R2)); in tally_prims_written()
111 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R1)); in tally_prims_written()
112 OUT_BATCH(MI_MATH_ALU0(SUB)); in tally_prims_written()
113 OUT_BATCH(MI_MATH_ALU2(STORE, R1, ACCU)); in tally_prims_written()
115 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0)); in tally_prims_written()
116 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R1)); in tally_prims_written()
117 OUT_BATCH(MI_MATH_ALU0(ADD)); in tally_prims_written()
118 OUT_BATCH(MI_MATH_ALU2(STORE, R0, ACCU)); in tally_prims_written()
131 OUT_BATCH(HSW_MI_MATH | (5 - 2)); in tally_prims_written()
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Dgen8_hs_state.c43 OUT_BATCH(_3DSTATE_HS << 16 | (9 - 2)); in gen8_upload_hs_state()
44 OUT_BATCH(SET_FIELD(DIV_ROUND_UP(stage_state->sampler_count, 4), in gen8_upload_hs_state()
48 OUT_BATCH(GEN7_HS_ENABLE | in gen8_upload_hs_state()
53 OUT_BATCH(stage_state->prog_offset); in gen8_upload_hs_state()
54 OUT_BATCH(0); in gen8_upload_hs_state()
60 OUT_BATCH(0); in gen8_upload_hs_state()
61 OUT_BATCH(0); in gen8_upload_hs_state()
63 OUT_BATCH(GEN7_HS_INCLUDE_VERTEX_HANDLES | in gen8_upload_hs_state()
66 OUT_BATCH(0); /* MBZ */ in gen8_upload_hs_state()
70 OUT_BATCH(_3DSTATE_HS << 16 | (9 - 2)); in gen8_upload_hs_state()
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Dgen8_gs_state.c52 OUT_BATCH(_3DSTATE_GS << 16 | (10 - 2)); in gen8_upload_gs_state()
53 OUT_BATCH(stage_state->prog_offset); in gen8_upload_gs_state()
54 OUT_BATCH(0); in gen8_upload_gs_state()
55 OUT_BATCH(gs_prog_data->vertices_in | in gen8_upload_gs_state()
66 OUT_BATCH(0); in gen8_upload_gs_state()
67 OUT_BATCH(0); in gen8_upload_gs_state()
71 OUT_BATCH(((gs_prog_data->output_vertex_size_hwords * 2 - 1) << in gen8_upload_gs_state()
109 OUT_BATCH(dw7); in gen8_upload_gs_state()
112 OUT_BATCH(dw8); in gen8_upload_gs_state()
115 OUT_BATCH(vue_prog_data->cull_distance_mask | in gen8_upload_gs_state()
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Dbrw_compute.c58 OUT_BATCH(MI_LOAD_REGISTER_IMM | (7 - 2)); in prepare_indirect_gpgpu_walker()
59 OUT_BATCH(MI_PREDICATE_SRC0 + 4); in prepare_indirect_gpgpu_walker()
60 OUT_BATCH(0u); in prepare_indirect_gpgpu_walker()
61 OUT_BATCH(MI_PREDICATE_SRC1 + 0); in prepare_indirect_gpgpu_walker()
62 OUT_BATCH(0u); in prepare_indirect_gpgpu_walker()
63 OUT_BATCH(MI_PREDICATE_SRC1 + 4); in prepare_indirect_gpgpu_walker()
64 OUT_BATCH(0u); in prepare_indirect_gpgpu_walker()
74 OUT_BATCH(GEN7_MI_PREDICATE | in prepare_indirect_gpgpu_walker()
87 OUT_BATCH(GEN7_MI_PREDICATE | in prepare_indirect_gpgpu_walker()
100 OUT_BATCH(GEN7_MI_PREDICATE | in prepare_indirect_gpgpu_walker()
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Dgen8_draw_upload.c97 OUT_BATCH(_3DSTATE_VF_SGVS << 16 | (2 - 2)); in gen8_emit_vertices()
98 OUT_BATCH(dw1); in gen8_emit_vertices()
102 OUT_BATCH(_3DSTATE_VF_INSTANCING << 16 | (3 - 2)); in gen8_emit_vertices()
103 OUT_BATCH(vue | GEN8_VF_INSTANCING_ENABLE); in gen8_emit_vertices()
104 OUT_BATCH(0); in gen8_emit_vertices()
108 OUT_BATCH(_3DSTATE_VF_SGVS << 16 | (2 - 2)); in gen8_emit_vertices()
109 OUT_BATCH(0); in gen8_emit_vertices()
138 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | (3 - 2)); in gen8_emit_vertices()
139 OUT_BATCH((0 << GEN6_VE0_INDEX_SHIFT) | in gen8_emit_vertices()
143 OUT_BATCH((BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_0_SHIFT) | in gen8_emit_vertices()
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Dgen7_misc_state.c105 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); in gen7_emit_depth_stencil_hiz()
108 OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) | in gen7_emit_depth_stencil_hiz()
121 OUT_BATCH(0); in gen7_emit_depth_stencil_hiz()
125 OUT_BATCH(((width - 1) << 4) | in gen7_emit_depth_stencil_hiz()
130 OUT_BATCH(((depth - 1) << 21) | in gen7_emit_depth_stencil_hiz()
135 OUT_BATCH(0); in gen7_emit_depth_stencil_hiz()
138 OUT_BATCH((depth - 1) << 21); in gen7_emit_depth_stencil_hiz()
143 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2)); in gen7_emit_depth_stencil_hiz()
144 OUT_BATCH(0); in gen7_emit_depth_stencil_hiz()
145 OUT_BATCH(0); in gen7_emit_depth_stencil_hiz()
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Dgen6_vs_state.c98 OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2)); in upload_vs_state()
99 OUT_BATCH(0); in upload_vs_state()
100 OUT_BATCH(0); in upload_vs_state()
101 OUT_BATCH(0); in upload_vs_state()
102 OUT_BATCH(0); in upload_vs_state()
106 OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | in upload_vs_state()
112 OUT_BATCH(stage_state->push_const_offset + in upload_vs_state()
114 OUT_BATCH(0); in upload_vs_state()
115 OUT_BATCH(0); in upload_vs_state()
116 OUT_BATCH(0); in upload_vs_state()
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Dgen6_depth_state.c112 OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); in gen6_emit_depth_stencil_hiz()
115 OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) | in gen6_emit_depth_stencil_hiz()
130 OUT_BATCH(0); in gen6_emit_depth_stencil_hiz()
134 OUT_BATCH(((width - 1) << 6) | in gen6_emit_depth_stencil_hiz()
139 OUT_BATCH((depth - 1) << 21 | in gen6_emit_depth_stencil_hiz()
144 OUT_BATCH(0); in gen6_emit_depth_stencil_hiz()
148 OUT_BATCH(0); in gen6_emit_depth_stencil_hiz()
175 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); in gen6_emit_depth_stencil_hiz()
176 OUT_BATCH(hiz_mt->pitch - 1); in gen6_emit_depth_stencil_hiz()
183 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); in gen6_emit_depth_stencil_hiz()
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Dgen8_sol_state.c58 OUT_BATCH(_3DSTATE_SO_BUFFER << 16 | (8 - 2)); in gen8_upload_3dstate_so_buffers()
59 OUT_BATCH((i << SO_BUFFER_INDEX_SHIFT)); in gen8_upload_3dstate_so_buffers()
60 OUT_BATCH(0); in gen8_upload_3dstate_so_buffers()
61 OUT_BATCH(0); in gen8_upload_3dstate_so_buffers()
62 OUT_BATCH(0); in gen8_upload_3dstate_so_buffers()
63 OUT_BATCH(0); in gen8_upload_3dstate_so_buffers()
64 OUT_BATCH(0); in gen8_upload_3dstate_so_buffers()
65 OUT_BATCH(0); in gen8_upload_3dstate_so_buffers()
78 OUT_BATCH(_3DSTATE_SO_BUFFER << 16 | (8 - 2)); in gen8_upload_3dstate_so_buffers()
79 OUT_BATCH(GEN8_SO_BUFFER_ENABLE | (i << SO_BUFFER_INDEX_SHIFT) | in gen8_upload_3dstate_so_buffers()
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Dgen8_multisample_state.c41 OUT_BATCH(GEN8_3DSTATE_MULTISAMPLE << 16 | (2 - 2)); in gen8_emit_3dstate_multisample()
42 OUT_BATCH(MS_PIXEL_LOCATION_CENTER | log2_samples << 1); in gen8_emit_3dstate_multisample()
53 OUT_BATCH(_3DSTATE_SAMPLE_PATTERN << 16 | (9 - 2)); in gen8_emit_3dstate_sample_pattern()
56 OUT_BATCH(brw_multisample_positions_16x[0]); /* positions 3, 2, 1, 0 */ in gen8_emit_3dstate_sample_pattern()
57 OUT_BATCH(brw_multisample_positions_16x[1]); /* positions 7, 6, 5, 4 */ in gen8_emit_3dstate_sample_pattern()
58 OUT_BATCH(brw_multisample_positions_16x[2]); /* positions 11, 10, 9, 8 */ in gen8_emit_3dstate_sample_pattern()
59 OUT_BATCH(brw_multisample_positions_16x[3]); /* positions 15, 14, 13, 12 */ in gen8_emit_3dstate_sample_pattern()
62 OUT_BATCH(brw_multisample_positions_8x[1]); /* sample positions 7654 */ in gen8_emit_3dstate_sample_pattern()
63 OUT_BATCH(brw_multisample_positions_8x[0]); /* sample positions 3210 */ in gen8_emit_3dstate_sample_pattern()
66 OUT_BATCH(brw_multisample_positions_4x); in gen8_emit_3dstate_sample_pattern()
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Dgen7_hs_state.c77 OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2)); in gen7_upload_hs_state()
78 OUT_BATCH(SET_FIELD(DIV_ROUND_UP(stage_state->sampler_count, 4), in gen7_upload_hs_state()
83 OUT_BATCH(GEN7_HS_ENABLE | in gen7_upload_hs_state()
87 OUT_BATCH(stage_state->prog_offset); in gen7_upload_hs_state()
93 OUT_BATCH(0); in gen7_upload_hs_state()
95 OUT_BATCH(GEN7_HS_INCLUDE_VERTEX_HANDLES | in gen7_upload_hs_state()
99 OUT_BATCH(0); in gen7_upload_hs_state()
103 OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2)); in gen7_upload_hs_state()
104 OUT_BATCH(0); in gen7_upload_hs_state()
105 OUT_BATCH(0); in gen7_upload_hs_state()
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Dintel_batchbuffer.c261 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2)); in brw_finish_batch()
262 OUT_BATCH(brw->cc.state_offset | 1); in brw_finish_batch()
508 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (4 - 2)); in load_sized_register_mem()
509 OUT_BATCH(reg + i * 4); in load_sized_register_mem()
516 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2)); in load_sized_register_mem()
517 OUT_BATCH(reg + i * 4); in load_sized_register_mem()
555 OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2)); in brw_store_register_mem32()
556 OUT_BATCH(reg); in brw_store_register_mem32()
562 OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2)); in brw_store_register_mem32()
563 OUT_BATCH(reg); in brw_store_register_mem32()
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Dgen7_gs_state.c62 OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2)); in upload_gs_state()
63 OUT_BATCH(stage_state->prog_offset); in upload_gs_state()
64 OUT_BATCH(((ALIGN(stage_state->sampler_count, 4)/4) << in upload_gs_state()
74 OUT_BATCH(0); in upload_gs_state()
135 OUT_BATCH(dw4); in upload_gs_state()
136 OUT_BATCH(dw5); in upload_gs_state()
137 OUT_BATCH(dw6); in upload_gs_state()
141 OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2)); in upload_gs_state()
142 OUT_BATCH(0); /* prog_bo */ in upload_gs_state()
143 OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) | in upload_gs_state()
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Dbrw_binding_tables.c137 OUT_BATCH(packet_name << 16 | (2 - 2)); in brw_upload_binding_table()
141 OUT_BATCH(brw->use_resource_streamer ? in brw_upload_binding_table()
303 OUT_BATCH(stage_to_bt_edit[stage] << 16 | (3 - 2)); in gen7_edit_hw_binding_table_entry()
304 OUT_BATCH(BRW_BINDING_TABLE_EDIT_TARGET_ALL); in gen7_edit_hw_binding_table_entry()
305 OUT_BATCH(dw2); in gen7_edit_hw_binding_table_entry()
327 OUT_BATCH(stage_to_bt_edit[stage] << 16 | num_surfaces); in gen7_update_binding_table_from_array()
328 OUT_BATCH(BRW_BINDING_TABLE_EDIT_TARGET_ALL); in gen7_update_binding_table_from_array()
333 OUT_BATCH(dw2); in gen7_update_binding_table_from_array()
358 OUT_BATCH(_3DSTATE_BINDING_TABLE_POOL_ALLOC << 16 | (pkt_len - 2)); in gen7_disable_hw_binding_tables()
360 OUT_BATCH(0); in gen7_disable_hw_binding_tables()
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Dgen6_wm_state.c94 OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (5 - 2)); in gen6_upload_wm_state()
95 OUT_BATCH(0); in gen6_upload_wm_state()
96 OUT_BATCH(0); in gen6_upload_wm_state()
97 OUT_BATCH(0); in gen6_upload_wm_state()
98 OUT_BATCH(0); in gen6_upload_wm_state()
102 OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | in gen6_upload_wm_state()
108 OUT_BATCH(stage_state->push_const_offset + in gen6_upload_wm_state()
110 OUT_BATCH(0); in gen6_upload_wm_state()
111 OUT_BATCH(0); in gen6_upload_wm_state()
112 OUT_BATCH(0); in gen6_upload_wm_state()
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Dgen7_ds_state.c80 OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2)); in gen7_upload_ds_state()
81 OUT_BATCH(stage_state->prog_offset); in gen7_upload_ds_state()
82 OUT_BATCH(SET_FIELD(DIV_ROUND_UP(stage_state->sampler_count, 4), in gen7_upload_ds_state()
91 OUT_BATCH(0); in gen7_upload_ds_state()
93 OUT_BATCH(SET_FIELD(prog_data->dispatch_grf_start_reg, in gen7_upload_ds_state()
98 OUT_BATCH(GEN7_DS_ENABLE | in gen7_upload_ds_state()
106 OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2)); in gen7_upload_ds_state()
107 OUT_BATCH(0); in gen7_upload_ds_state()
108 OUT_BATCH(0); in gen7_upload_ds_state()
109 OUT_BATCH(0); in gen7_upload_ds_state()
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/external/mesa3d/src/gallium/drivers/i915/
Di915_clear.c133 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT); in i915_clear_emit()
135 OUT_BATCH(_3DSTATE_CLEAR_PARAMETERS); in i915_clear_emit()
136 OUT_BATCH(CLEARPARAM_WRITE_COLOR | CLEARPARAM_CLEAR_RECT); in i915_clear_emit()
138 OUT_BATCH(clear_color); in i915_clear_emit()
139 OUT_BATCH(clear_depth); in i915_clear_emit()
141 OUT_BATCH(clear_color8888); in i915_clear_emit()
143 OUT_BATCH(clear_stencil); in i915_clear_emit()
145 OUT_BATCH(_3DPRIMITIVE | PRIM3D_CLEAR_RECT | 5); in i915_clear_emit()
153 OUT_BATCH(_3DSTATE_CLEAR_PARAMETERS); in i915_clear_emit()
154 OUT_BATCH((clear_params & ~CLEARPARAM_WRITE_COLOR) | in i915_clear_emit()
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Di915_state_emit.c68 OUT_BATCH(MI_FLUSH | FLUSH_MAP_CACHE); in emit_flush()
70 OUT_BATCH(MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE); in emit_flush()
172 OUT_BATCH(fixup_imm); in emit_immediate_s5()
192 OUT_BATCH(imm); in emit_immediate_s6()
207 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | in emit_immediate()
215 OUT_BATCH(0); in emit_immediate()
225 OUT_BATCH(i915->current.immediate[i]); in emit_immediate()
242 OUT_BATCH(i915->current.dynamic[i]); in emit_dynamic()
274 OUT_BATCH(_3DSTATE_BUF_INFO_CMD); in emit_static()
275 OUT_BATCH(i915->current.cbuf_flags); in emit_static()
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/external/mesa3d/src/mesa/drivers/dri/i915/
Di830_vtbl.c304 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD); in i830_emit_invarient_state()
305 OUT_BATCH(0); in i830_emit_invarient_state()
307 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD); in i830_emit_invarient_state()
308 OUT_BATCH(0); in i830_emit_invarient_state()
310 OUT_BATCH(_3DSTATE_DFLT_Z_CMD); in i830_emit_invarient_state()
311 OUT_BATCH(0); in i830_emit_invarient_state()
313 OUT_BATCH(_3DSTATE_FOG_MODE_CMD); in i830_emit_invarient_state()
314 OUT_BATCH(FOGFUNC_ENABLE | in i830_emit_invarient_state()
316 OUT_BATCH(0); in i830_emit_invarient_state()
317 OUT_BATCH(0); in i830_emit_invarient_state()
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