1 /*
2 * Copyright © 2009 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #include "brw_context.h"
29 #include "brw_state.h"
30 #include "brw_defines.h"
31 #include "brw_util.h"
32 #include "program/prog_parameter.h"
33 #include "program/prog_statevars.h"
34 #include "main/shaderapi.h"
35 #include "intel_batchbuffer.h"
36
37 static void
gen6_upload_vs_push_constants(struct brw_context * brw)38 gen6_upload_vs_push_constants(struct brw_context *brw)
39 {
40 struct brw_stage_state *stage_state = &brw->vs.base;
41
42 /* _BRW_NEW_VERTEX_PROGRAM */
43 const struct brw_program *vp = brw_program_const(brw->vertex_program);
44 /* BRW_NEW_VS_PROG_DATA */
45 const struct brw_stage_prog_data *prog_data = brw->vs.base.prog_data;
46
47 _mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_VERTEX);
48 gen6_upload_push_constants(brw, &vp->program, prog_data, stage_state,
49 AUB_TRACE_VS_CONSTANTS);
50
51 if (brw->gen >= 7) {
52 if (brw->gen == 7 && !brw->is_haswell && !brw->is_baytrail)
53 gen7_emit_vs_workaround_flush(brw);
54
55 gen7_upload_constant_state(brw, stage_state, true /* active */,
56 _3DSTATE_CONSTANT_VS);
57 }
58 }
59
60 const struct brw_tracked_state gen6_vs_push_constants = {
61 .dirty = {
62 .mesa = _NEW_PROGRAM_CONSTANTS |
63 _NEW_TRANSFORM,
64 .brw = BRW_NEW_BATCH |
65 BRW_NEW_BLORP |
66 BRW_NEW_PUSH_CONSTANT_ALLOCATION |
67 BRW_NEW_VERTEX_PROGRAM |
68 BRW_NEW_VS_PROG_DATA,
69 },
70 .emit = gen6_upload_vs_push_constants,
71 };
72
73 static void
upload_vs_state(struct brw_context * brw)74 upload_vs_state(struct brw_context *brw)
75 {
76 const struct gen_device_info *devinfo = &brw->screen->devinfo;
77 const struct brw_stage_state *stage_state = &brw->vs.base;
78 const struct brw_stage_prog_data *prog_data = stage_state->prog_data;
79 const struct brw_vue_prog_data *vue_prog_data =
80 brw_vue_prog_data(stage_state->prog_data);
81 uint32_t floating_point_mode = 0;
82
83 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
84 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
85 *
86 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
87 * command that causes the VS Function Enable to toggle. Pipeline
88 * flush can be executed by sending a PIPE_CONTROL command with CS
89 * stall bit set and a post sync operation.
90 *
91 * We've already done such a flush at the start of state upload, so we
92 * don't need to do another one here.
93 */
94
95 if (stage_state->push_const_size == 0) {
96 /* Disable the push constant buffers. */
97 BEGIN_BATCH(5);
98 OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2));
99 OUT_BATCH(0);
100 OUT_BATCH(0);
101 OUT_BATCH(0);
102 OUT_BATCH(0);
103 ADVANCE_BATCH();
104 } else {
105 BEGIN_BATCH(5);
106 OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 |
107 GEN6_CONSTANT_BUFFER_0_ENABLE |
108 (5 - 2));
109 /* Pointer to the VS constant buffer. Covered by the set of
110 * state flags from gen6_upload_vs_constants
111 */
112 OUT_BATCH(stage_state->push_const_offset +
113 stage_state->push_const_size - 1);
114 OUT_BATCH(0);
115 OUT_BATCH(0);
116 OUT_BATCH(0);
117 ADVANCE_BATCH();
118 }
119
120 if (prog_data->use_alt_mode)
121 floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
122
123 BEGIN_BATCH(6);
124 OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
125 OUT_BATCH(stage_state->prog_offset);
126 OUT_BATCH(floating_point_mode |
127 ((ALIGN(stage_state->sampler_count, 4)/4) << GEN6_VS_SAMPLER_COUNT_SHIFT) |
128 ((prog_data->binding_table.size_bytes / 4) <<
129 GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
130
131 if (prog_data->total_scratch) {
132 OUT_RELOC(stage_state->scratch_bo,
133 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
134 ffs(stage_state->per_thread_scratch) - 11);
135 } else {
136 OUT_BATCH(0);
137 }
138
139 OUT_BATCH((prog_data->dispatch_grf_start_reg <<
140 GEN6_VS_DISPATCH_START_GRF_SHIFT) |
141 (vue_prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
142 (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
143
144 OUT_BATCH(((devinfo->max_vs_threads - 1) << GEN6_VS_MAX_THREADS_SHIFT) |
145 GEN6_VS_STATISTICS_ENABLE |
146 GEN6_VS_ENABLE);
147 ADVANCE_BATCH();
148
149 /* Based on my reading of the simulator, the VS constants don't get
150 * pulled into the VS FF unit until an appropriate pipeline flush
151 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
152 * references to them into a little FIFO. The flushes are common,
153 * but don't reliably happen between this and a 3DPRIMITIVE, causing
154 * the primitive to use the wrong constants. Then the FIFO
155 * containing the constant setup gets added to again on the next
156 * constants change, and eventually when a flush does happen the
157 * unit is overwhelmed by constant changes and dies.
158 *
159 * To avoid this, send a PIPE_CONTROL down the line that will
160 * update the unit immediately loading the constants. The flush
161 * type bits here were those set by the STATE_BASE_ADDRESS whose
162 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
163 * bug reports that led to this workaround, and may be more than
164 * what is strictly required to avoid the issue.
165 */
166 brw_emit_pipe_control_flush(brw,
167 PIPE_CONTROL_DEPTH_STALL |
168 PIPE_CONTROL_INSTRUCTION_INVALIDATE |
169 PIPE_CONTROL_STATE_CACHE_INVALIDATE);
170 }
171
172 const struct brw_tracked_state gen6_vs_state = {
173 .dirty = {
174 .mesa = _NEW_PROGRAM_CONSTANTS |
175 _NEW_TRANSFORM,
176 .brw = BRW_NEW_BATCH |
177 BRW_NEW_BLORP |
178 BRW_NEW_CONTEXT |
179 BRW_NEW_PUSH_CONSTANT_ALLOCATION |
180 BRW_NEW_VERTEX_PROGRAM |
181 BRW_NEW_VS_PROG_DATA,
182 },
183 .emit = upload_vs_state,
184 };
185