| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86GenFastISel.inc | 1443 …FastEmit_ISD_ADD_MVT_i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1446 return FastEmitInst_rr(X86::ADD8rr, X86::GR8RegisterClass, Op0, Op0IsKill, Op1, Op1IsKill);
1449 …astEmit_ISD_ADD_MVT_i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1452 return FastEmitInst_rr(X86::ADD16rr, X86::GR16RegisterClass, Op0, Op0IsKill, Op1, Op1IsKill);
1455 …astEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1458 return FastEmitInst_rr(X86::ADD32rr, X86::GR32RegisterClass, Op0, Op0IsKill, Op1, Op1IsKill);
1461 …astEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1464 return FastEmitInst_rr(X86::ADD64rr, X86::GR64RegisterClass, Op0, Op0IsKill, Op1, Op1IsKill);
1467 …tEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1471 return FastEmitInst_rr(X86::VPADDBrr, X86::VR128RegisterClass, Op0, Op0IsKill, Op1, Op1IsKill);
[all …]
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | FastISel.h | 178 unsigned Op1, bool Op1IsKill);
208 unsigned Op1, bool Op1IsKill,
255 unsigned Op1, bool Op1IsKill);
263 unsigned Op1, bool Op1IsKill,
296 unsigned Op1, bool Op1IsKill,
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| /external/llvm/include/llvm/CodeGen/ |
| D | FastISel.h | 351 bool Op0IsKill, unsigned Op1, bool Op1IsKill);
370 bool Op1IsKill, uint64_t Imm);
405 bool Op0IsKill, unsigned Op1, bool Op1IsKill);
411 bool Op0IsKill, unsigned Op1, bool Op1IsKill,
436 bool Op0IsKill, unsigned Op1, bool Op1IsKill,
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 349 bool Op1IsKill = hasTrivialKill(I->getOperand(1)); in SelectBinaryOp() local
352 Op1IsKill, CI->getZExtValue(), in SelectBinaryOp()
405 bool Op1IsKill = hasTrivialKill(I->getOperand(1)); in SelectBinaryOp() local
411 Op1, Op1IsKill); in SelectBinaryOp()
1133 unsigned Op1, bool Op1IsKill) { in FastEmitInst_rr() argument
1140 .addReg(Op1, Op1IsKill * RegState::Kill); in FastEmitInst_rr()
1144 .addReg(Op1, Op1IsKill * RegState::Kill); in FastEmitInst_rr()
1154 unsigned Op1, bool Op1IsKill, in FastEmitInst_rrr() argument
1162 .addReg(Op1, Op1IsKill * RegState::Kill) in FastEmitInst_rrr()
1167 .addReg(Op1, Op1IsKill * RegState::Kill) in FastEmitInst_rrr()
[all …]
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 412 bool Op1IsKill = hasTrivialKill(I->getOperand(1)); in selectBinaryOp() local
415 fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, Op1IsKill, in selectBinaryOp()
472 bool Op1IsKill = hasTrivialKill(I->getOperand(1)); in selectBinaryOp() local
476 ISDOpcode, Op0, Op0IsKill, Op1, Op1IsKill); in selectBinaryOp()
1839 bool Op1IsKill) { in fastEmitInst_rr() argument
1849 .addReg(Op1, getKillRegState(Op1IsKill)); in fastEmitInst_rr()
1853 .addReg(Op1, getKillRegState(Op1IsKill)); in fastEmitInst_rr()
1863 bool Op1IsKill, unsigned Op2, in fastEmitInst_rrr() argument
1875 .addReg(Op1, getKillRegState(Op1IsKill)) in fastEmitInst_rrr()
1880 .addReg(Op1, getKillRegState(Op1IsKill)) in fastEmitInst_rrr()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 117 unsigned Op1, bool Op1IsKill);
121 unsigned Op1, bool Op1IsKill,
134 unsigned Op1, bool Op1IsKill,
309 unsigned Op1, bool Op1IsKill) { in FastEmitInst_rr() argument
316 .addReg(Op1, Op1IsKill * RegState::Kill)); in FastEmitInst_rr()
320 .addReg(Op1, Op1IsKill * RegState::Kill)); in FastEmitInst_rr()
331 unsigned Op1, bool Op1IsKill, in FastEmitInst_rrr() argument
339 .addReg(Op1, Op1IsKill * RegState::Kill) in FastEmitInst_rrr()
344 .addReg(Op1, Op1IsKill * RegState::Kill) in FastEmitInst_rrr()
400 unsigned Op1, bool Op1IsKill, in FastEmitInst_rri() argument
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 212 unsigned Op1, bool Op1IsKill);
214 unsigned Op1, bool Op1IsKill);
216 unsigned Op1, bool Op1IsKill);
218 unsigned Op1Reg, bool Op1IsKill);
222 unsigned Op1Reg, bool Op1IsKill);
226 unsigned Op1Reg, bool Op1IsKill);
3869 unsigned Op1, bool Op1IsKill) { in emitMul_rr() argument
3884 return fastEmitInst_rrr(Opc, RC, Op0, Op0IsKill, Op1, Op1IsKill, in emitMul_rr()
3889 unsigned Op1, bool Op1IsKill) { in emitSMULL_rr() argument
3894 Op0, Op0IsKill, Op1, Op1IsKill, in emitSMULL_rr()
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 110 unsigned Op1, bool Op1IsKill);
118 unsigned Op1, bool Op1IsKill,
303 unsigned Op1, bool Op1IsKill) { in fastEmitInst_rr() argument
316 .addReg(Op1, Op1IsKill * RegState::Kill)); in fastEmitInst_rr()
320 .addReg(Op1, Op1IsKill * RegState::Kill)); in fastEmitInst_rr()
357 unsigned Op1, bool Op1IsKill, in fastEmitInst_rri() argument
370 .addReg(Op1, Op1IsKill * RegState::Kill) in fastEmitInst_rri()
375 .addReg(Op1, Op1IsKill * RegState::Kill) in fastEmitInst_rri()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 181 unsigned Op1, bool Op1IsKill);
1869 unsigned Op1, bool Op1IsKill) { in fastEmitInst_rr() argument
1883 .addReg(Op1, getKillRegState(Op1IsKill)) in fastEmitInst_rr()
1890 Op1IsKill); in fastEmitInst_rr()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 125 unsigned Op1, bool Op1IsKill);
2338 unsigned Op1, bool Op1IsKill) { in fastEmitInst_rr() argument
2344 Op1, Op1IsKill); in fastEmitInst_rr()
|