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Searched refs:OperandCycles (Results 1 – 19 of 19) sorted by relevance

/external/swiftshader/third_party/LLVM/include/llvm/MC/
DMCInstrItineraries.h113 const unsigned *OperandCycles; ///< Array of operand cycles selected variable
120 InstrItineraryData() : Stages(0), OperandCycles(0), Forwardings(0), in InstrItineraryData()
125 : Stages(S), OperandCycles(OS), Forwardings(F), Itineraries(I), in InstrItineraryData()
191 return (int)OperandCycles[FirstIdx + OperandIdx]; in getOperandCycle()
DMCSubtargetInfo.h35 const unsigned *OperandCycles; // Operand cycles variable
/external/llvm/include/llvm/MC/
DMCInstrItineraries.h113 const unsigned *OperandCycles; ///< Array of operand cycles selected variable
119 Stages(nullptr), OperandCycles(nullptr), in InstrItineraryData()
124 : SchedModel(SM), Stages(S), OperandCycles(OS), Forwardings(F), in InstrItineraryData()
178 return (int)OperandCycles[FirstIdx + OperandIdx]; in getOperandCycle()
DMCSubtargetInfo.h44 const unsigned *OperandCycles; // Itinerary operand cycles variable
/external/llvm/lib/MC/
DMCSubtargetInfo.cpp47 ReadAdvanceTable(RA), Stages(IS), OperandCycles(OC), ForwardingPaths(FP) { in MCSubtargetInfo()
103 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths); in getInstrItineraryForCPU()
108 InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles, in initInstrItins()
/external/swiftshader/third_party/LLVM/lib/MC/
DMCSubtargetInfo.cpp34 OperandCycles = OC; in InitMCSubtargetInfo()
94 return InstrItineraryData(Stages, OperandCycles, ForwardingPathes, in getInstrItineraryForCPU()
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetSchedule.td90 // OperandCycles are optional "cycle counts". They specify the cycle after
112 list<int> OperandCycles = operandcycles;
/external/llvm/include/llvm/Target/
DTargetItinerary.td93 // OperandCycles are optional "cycle counts". They specify the cycle after
116 list<int> OperandCycles = operandcycles;
/external/llvm/lib/Target/PowerPC/
DPPCScheduleA2.td164 // This is overriden by OperandCycles if the
DPPCScheduleG5.td122 // This is overriden by OperandCycles if the
DPPCScheduleE500mc.td315 // This is overriden by OperandCycles if the
DPPCScheduleE5500.td375 // This is overriden by OperandCycles if the
DPPCScheduleP7.td386 // This is overriden by OperandCycles if the
DPPCScheduleP8.td395 // This is overriden by OperandCycles if the
DPPCSchedule440.td601 // This is overriden by OperandCycles if the
/external/llvm/lib/Target/X86/
DX86ScheduleAtom.td540 let LoadLatency = 3; // Expected cycles, may be overriden by OperandCycles.
541 let HighLatency = 30;// Expected, may be overriden by OperandCycles.
/external/llvm/lib/Target/AArch64/
DAArch64SchedA53.td23 // This is overriden by OperandCycles if the
/external/llvm/lib/Target/ARM/
DARMScheduleA8.td1069 // This is overriden by OperandCycles if the
DARMScheduleA9.td1892 // This is overriden by OperandCycles if the