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1//===- X86ScheduleAtom.td - X86 Atom Scheduling Definitions -*- tablegen -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the Intel Atom
11// in order (Saltwell-32nm/Bonnell-45nm) processors.
12//
13//===----------------------------------------------------------------------===//
14
15//
16// Scheduling information derived from the "Intel 64 and IA32 Architectures
17// Optimization Reference Manual", Chapter 13, Section 4.
18// Functional Units
19//    Port 0
20def Port0 : FuncUnit; // ALU: ALU0, shift/rotate, load/store
21                      // SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide
22def Port1 : FuncUnit; // ALU: ALU1, bit processing, jump, and LEA
23                      // SIMD/FP: SIMD ALU, FP Adder
24
25def AtomItineraries : ProcessorItineraries<
26  [ Port0, Port1 ],
27  [], [
28  // P0 only
29  // InstrItinData<class, [InstrStage<N, [P0]>] >,
30  // P0 or P1
31  // InstrItinData<class, [InstrStage<N, [P0, P1]>] >,
32  // P0 and P1
33  // InstrItinData<class, [InstrStage<N, [P0], 0>,  InstrStage<N, [P1]>] >,
34  //
35  // Default is 1 cycle, port0 or port1
36  InstrItinData<IIC_ALU_MEM, [InstrStage<1, [Port0]>] >,
37  InstrItinData<IIC_ALU_NONMEM, [InstrStage<1, [Port0, Port1]>] >,
38  InstrItinData<IIC_LEA, [InstrStage<1, [Port1]>] >,
39  InstrItinData<IIC_LEA_16, [InstrStage<2, [Port0, Port1]>] >,
40  // mul
41  InstrItinData<IIC_MUL8, [InstrStage<7, [Port0, Port1]>] >,
42  InstrItinData<IIC_MUL16_MEM, [InstrStage<8, [Port0, Port1]>] >,
43  InstrItinData<IIC_MUL16_REG, [InstrStage<7, [Port0, Port1]>] >,
44  InstrItinData<IIC_MUL32_MEM, [InstrStage<7, [Port0, Port1]>] >,
45  InstrItinData<IIC_MUL32_REG, [InstrStage<6, [Port0, Port1]>] >,
46  InstrItinData<IIC_MUL64, [InstrStage<12, [Port0, Port1]>] >,
47  // imul by al, ax, eax, rax
48  InstrItinData<IIC_IMUL8, [InstrStage<7, [Port0, Port1]>] >,
49  InstrItinData<IIC_IMUL16_MEM, [InstrStage<8, [Port0, Port1]>] >,
50  InstrItinData<IIC_IMUL16_REG, [InstrStage<7, [Port0, Port1]>] >,
51  InstrItinData<IIC_IMUL32_MEM, [InstrStage<7, [Port0, Port1]>] >,
52  InstrItinData<IIC_IMUL32_REG, [InstrStage<6, [Port0, Port1]>] >,
53  InstrItinData<IIC_IMUL64, [InstrStage<12, [Port0, Port1]>] >,
54  // imul reg by reg|mem
55  InstrItinData<IIC_IMUL16_RM, [InstrStage<7, [Port0, Port1]>] >,
56  InstrItinData<IIC_IMUL16_RR, [InstrStage<6, [Port0, Port1]>] >,
57  InstrItinData<IIC_IMUL32_RM, [InstrStage<5, [Port0]>] >,
58  InstrItinData<IIC_IMUL32_RR, [InstrStage<5, [Port0]>] >,
59  InstrItinData<IIC_IMUL64_RM, [InstrStage<12, [Port0, Port1]>] >,
60  InstrItinData<IIC_IMUL64_RR, [InstrStage<12, [Port0, Port1]>] >,
61  // imul reg = reg/mem * imm
62  InstrItinData<IIC_IMUL16_RRI, [InstrStage<6, [Port0, Port1]>] >,
63  InstrItinData<IIC_IMUL32_RRI, [InstrStage<5, [Port0]>] >,
64  InstrItinData<IIC_IMUL64_RRI, [InstrStage<14, [Port0, Port1]>] >,
65  InstrItinData<IIC_IMUL16_RMI, [InstrStage<7, [Port0, Port1]>] >,
66  InstrItinData<IIC_IMUL32_RMI, [InstrStage<5, [Port0]>] >,
67  InstrItinData<IIC_IMUL64_RMI, [InstrStage<14, [Port0, Port1]>] >,
68  // idiv
69  InstrItinData<IIC_IDIV8, [InstrStage<62, [Port0, Port1]>] >,
70  InstrItinData<IIC_IDIV16, [InstrStage<62, [Port0, Port1]>] >,
71  InstrItinData<IIC_IDIV32, [InstrStage<62, [Port0, Port1]>] >,
72  InstrItinData<IIC_IDIV64, [InstrStage<130, [Port0, Port1]>] >,
73  // div
74  InstrItinData<IIC_DIV8_REG, [InstrStage<50, [Port0, Port1]>] >,
75  InstrItinData<IIC_DIV8_MEM, [InstrStage<68, [Port0, Port1]>] >,
76  InstrItinData<IIC_DIV16, [InstrStage<50, [Port0, Port1]>] >,
77  InstrItinData<IIC_DIV32, [InstrStage<50, [Port0, Port1]>] >,
78  InstrItinData<IIC_DIV64, [InstrStage<130, [Port0, Port1]>] >,
79  // neg/not/inc/dec
80  InstrItinData<IIC_UNARY_REG, [InstrStage<1, [Port0, Port1]>] >,
81  InstrItinData<IIC_UNARY_MEM, [InstrStage<1, [Port0]>] >,
82  // add/sub/and/or/xor/cmp/test
83  InstrItinData<IIC_BIN_NONMEM, [InstrStage<1, [Port0, Port1]>] >,
84  InstrItinData<IIC_BIN_MEM, [InstrStage<1, [Port0]>] >,
85  // adc/sbc
86  InstrItinData<IIC_BIN_CARRY_NONMEM, [InstrStage<1, [Port0, Port1]>] >,
87  InstrItinData<IIC_BIN_CARRY_MEM, [InstrStage<1, [Port0]>] >,
88  // shift/rotate
89  InstrItinData<IIC_SR, [InstrStage<1, [Port0]>] >,
90  // shift double
91  InstrItinData<IIC_SHD16_REG_IM, [InstrStage<6, [Port0, Port1]>] >,
92  InstrItinData<IIC_SHD16_REG_CL, [InstrStage<6, [Port0, Port1]>] >,
93  InstrItinData<IIC_SHD16_MEM_IM, [InstrStage<6, [Port0, Port1]>] >,
94  InstrItinData<IIC_SHD16_MEM_CL, [InstrStage<6, [Port0, Port1]>] >,
95  InstrItinData<IIC_SHD32_REG_IM, [InstrStage<2, [Port0, Port1]>] >,
96  InstrItinData<IIC_SHD32_REG_CL, [InstrStage<2, [Port0, Port1]>] >,
97  InstrItinData<IIC_SHD32_MEM_IM, [InstrStage<4, [Port0, Port1]>] >,
98  InstrItinData<IIC_SHD32_MEM_CL, [InstrStage<4, [Port0, Port1]>] >,
99  InstrItinData<IIC_SHD64_REG_IM, [InstrStage<9, [Port0, Port1]>] >,
100  InstrItinData<IIC_SHD64_REG_CL, [InstrStage<8, [Port0, Port1]>] >,
101  InstrItinData<IIC_SHD64_MEM_IM, [InstrStage<9, [Port0, Port1]>] >,
102  InstrItinData<IIC_SHD64_MEM_CL, [InstrStage<9, [Port0, Port1]>] >,
103  // cmov
104  InstrItinData<IIC_CMOV16_RM, [InstrStage<1, [Port0]>] >,
105  InstrItinData<IIC_CMOV16_RR, [InstrStage<1, [Port0, Port1]>] >,
106  InstrItinData<IIC_CMOV32_RM, [InstrStage<1, [Port0]>] >,
107  InstrItinData<IIC_CMOV32_RR, [InstrStage<1, [Port0, Port1]>] >,
108  InstrItinData<IIC_CMOV64_RM, [InstrStage<1, [Port0]>] >,
109  InstrItinData<IIC_CMOV64_RR, [InstrStage<1, [Port0, Port1]>] >,
110  // set
111  InstrItinData<IIC_SET_M, [InstrStage<2, [Port0, Port1]>] >,
112  InstrItinData<IIC_SET_R, [InstrStage<1, [Port0, Port1]>] >,
113  // jcc
114  InstrItinData<IIC_Jcc, [InstrStage<1, [Port1]>] >,
115  // jcxz/jecxz/jrcxz
116  InstrItinData<IIC_JCXZ, [InstrStage<4, [Port0, Port1]>] >,
117  // jmp rel
118  InstrItinData<IIC_JMP_REL, [InstrStage<1, [Port1]>] >,
119  // jmp indirect
120  InstrItinData<IIC_JMP_REG, [InstrStage<1, [Port1]>] >,
121  InstrItinData<IIC_JMP_MEM, [InstrStage<2, [Port0, Port1]>] >,
122  // jmp far
123  InstrItinData<IIC_JMP_FAR_MEM, [InstrStage<32, [Port0, Port1]>] >,
124  InstrItinData<IIC_JMP_FAR_PTR, [InstrStage<31, [Port0, Port1]>] >,
125  // loop/loope/loopne
126  InstrItinData<IIC_LOOP, [InstrStage<18, [Port0, Port1]>] >,
127  InstrItinData<IIC_LOOPE, [InstrStage<8, [Port0, Port1]>] >,
128  InstrItinData<IIC_LOOPNE, [InstrStage<17, [Port0, Port1]>] >,
129  // call - all but reg/imm
130  InstrItinData<IIC_CALL_RI, [InstrStage<1, [Port0], 0>,
131                              InstrStage<1, [Port1]>] >,
132  InstrItinData<IIC_CALL_MEM, [InstrStage<15, [Port0, Port1]>] >,
133  InstrItinData<IIC_CALL_FAR_MEM, [InstrStage<40, [Port0, Port1]>] >,
134  InstrItinData<IIC_CALL_FAR_PTR, [InstrStage<39, [Port0, Port1]>] >,
135  //ret
136  InstrItinData<IIC_RET, [InstrStage<79, [Port0, Port1]>] >,
137  InstrItinData<IIC_RET_IMM, [InstrStage<1, [Port0], 0>,  InstrStage<1, [Port1]>] >,
138  //sign extension movs
139  InstrItinData<IIC_MOVSX,[InstrStage<1, [Port0] >] >,
140  InstrItinData<IIC_MOVSX_R16_R8, [InstrStage<2, [Port0, Port1]>] >,
141  InstrItinData<IIC_MOVSX_R16_M8, [InstrStage<3, [Port0, Port1]>] >,
142  InstrItinData<IIC_MOVSX_R16_R16, [InstrStage<1, [Port0, Port1]>] >,
143  InstrItinData<IIC_MOVSX_R32_R32, [InstrStage<1, [Port0, Port1]>] >,
144  //zero extension movs
145  InstrItinData<IIC_MOVZX,[InstrStage<1, [Port0]>] >,
146  InstrItinData<IIC_MOVZX_R16_R8, [InstrStage<2, [Port0, Port1]>] >,
147  InstrItinData<IIC_MOVZX_R16_M8, [InstrStage<3, [Port0, Port1]>] >,
148
149  InstrItinData<IIC_REP_MOVS, [InstrStage<75, [Port0, Port1]>] >,
150  InstrItinData<IIC_REP_STOS, [InstrStage<74, [Port0, Port1]>] >,
151
152  // SSE binary operations
153  // arithmetic fp scalar
154  InstrItinData<IIC_SSE_ALU_F32S_RR, [InstrStage<5, [Port1]>] >,
155  InstrItinData<IIC_SSE_ALU_F32S_RM, [InstrStage<5, [Port0], 0>,
156                                   InstrStage<5, [Port1]>] >,
157  InstrItinData<IIC_SSE_ALU_F64S_RR, [InstrStage<5, [Port1]>] >,
158  InstrItinData<IIC_SSE_ALU_F64S_RM, [InstrStage<5, [Port0], 0>,
159                                   InstrStage<5, [Port1]>] >,
160  InstrItinData<IIC_SSE_MUL_F32S_RR, [InstrStage<4, [Port0]>] >,
161  InstrItinData<IIC_SSE_MUL_F32S_RM, [InstrStage<4, [Port0]>] >,
162  InstrItinData<IIC_SSE_MUL_F64S_RR, [InstrStage<5, [Port0]>] >,
163  InstrItinData<IIC_SSE_MUL_F64S_RM, [InstrStage<5, [Port0]>] >,
164  InstrItinData<IIC_SSE_DIV_F32S_RR, [InstrStage<34, [Port0, Port1]>] >,
165  InstrItinData<IIC_SSE_DIV_F32S_RM, [InstrStage<34, [Port0, Port1]>] >,
166  InstrItinData<IIC_SSE_DIV_F64S_RR, [InstrStage<62, [Port0, Port1]>] >,
167  InstrItinData<IIC_SSE_DIV_F64S_RM, [InstrStage<62, [Port0, Port1]>] >,
168
169  InstrItinData<IIC_SSE_COMIS_RR, [InstrStage<9, [Port0, Port1]>] >,
170  InstrItinData<IIC_SSE_COMIS_RM, [InstrStage<10, [Port0, Port1]>] >,
171
172  InstrItinData<IIC_SSE_HADDSUB_RR, [InstrStage<8, [Port0, Port1]>] >,
173  InstrItinData<IIC_SSE_HADDSUB_RM, [InstrStage<9, [Port0, Port1]>] >,
174
175  // arithmetic fp parallel
176  InstrItinData<IIC_SSE_ALU_F32P_RR, [InstrStage<5, [Port1]>] >,
177  InstrItinData<IIC_SSE_ALU_F32P_RM, [InstrStage<5, [Port0], 0>,
178                                   InstrStage<5, [Port1]>] >,
179  InstrItinData<IIC_SSE_ALU_F64P_RR, [InstrStage<6, [Port0, Port1]>] >,
180  InstrItinData<IIC_SSE_ALU_F64P_RM, [InstrStage<7, [Port0, Port1]>] >,
181  InstrItinData<IIC_SSE_MUL_F32P_RR, [InstrStage<5, [Port0]>] >,
182  InstrItinData<IIC_SSE_MUL_F32P_RM, [InstrStage<5, [Port0]>] >,
183  InstrItinData<IIC_SSE_MUL_F64P_RR, [InstrStage<9, [Port0, Port1]>] >,
184  InstrItinData<IIC_SSE_MUL_F64P_RM, [InstrStage<10, [Port0, Port1]>] >,
185  InstrItinData<IIC_SSE_DIV_F32P_RR, [InstrStage<70, [Port0, Port1]>] >,
186  InstrItinData<IIC_SSE_DIV_F32P_RM, [InstrStage<70, [Port0, Port1]>] >,
187  InstrItinData<IIC_SSE_DIV_F64P_RR, [InstrStage<125, [Port0, Port1]>] >,
188  InstrItinData<IIC_SSE_DIV_F64P_RM, [InstrStage<125, [Port0, Port1]>] >,
189
190  // bitwise parallel
191  InstrItinData<IIC_SSE_BIT_P_RR, [InstrStage<1, [Port0, Port1]>] >,
192  InstrItinData<IIC_SSE_BIT_P_RM, [InstrStage<1, [Port0]>] >,
193
194  // arithmetic int parallel
195  InstrItinData<IIC_SSE_INTALU_P_RR, [InstrStage<1, [Port0, Port1]>] >,
196  InstrItinData<IIC_SSE_INTALU_P_RM, [InstrStage<1, [Port0]>] >,
197  InstrItinData<IIC_SSE_INTALUQ_P_RR, [InstrStage<2, [Port0, Port1]>] >,
198  InstrItinData<IIC_SSE_INTALUQ_P_RM, [InstrStage<3, [Port0, Port1]>] >,
199
200  // multiply int parallel
201  InstrItinData<IIC_SSE_INTMUL_P_RR, [InstrStage<5, [Port0]>] >,
202  InstrItinData<IIC_SSE_INTMUL_P_RM, [InstrStage<5, [Port0]>] >,
203
204  // shift parallel
205  InstrItinData<IIC_SSE_INTSH_P_RR, [InstrStage<2, [Port0, Port1]>] >,
206  InstrItinData<IIC_SSE_INTSH_P_RM, [InstrStage<3, [Port0, Port1]>] >,
207  InstrItinData<IIC_SSE_INTSH_P_RI, [InstrStage<1, [Port0, Port1]>] >,
208
209  InstrItinData<IIC_SSE_INTSHDQ_P_RI, [InstrStage<1, [Port0, Port1]>] >,
210
211  InstrItinData<IIC_SSE_SHUFP, [InstrStage<1, [Port0]>] >,
212  InstrItinData<IIC_SSE_PSHUF_RI, [InstrStage<1, [Port0]>] >,
213  InstrItinData<IIC_SSE_PSHUF_MI, [InstrStage<1, [Port0]>] >,
214
215  InstrItinData<IIC_SSE_UNPCK, [InstrStage<1, [Port0]>] >,
216
217  InstrItinData<IIC_SSE_SQRTPS_RR, [InstrStage<70, [Port0, Port1]>] >,
218  InstrItinData<IIC_SSE_SQRTPS_RM, [InstrStage<70, [Port0, Port1]>] >,
219  InstrItinData<IIC_SSE_SQRTSS_RR, [InstrStage<34, [Port0, Port1]>] >,
220  InstrItinData<IIC_SSE_SQRTSS_RM, [InstrStage<34, [Port0, Port1]>] >,
221
222  InstrItinData<IIC_SSE_SQRTPD_RR, [InstrStage<125, [Port0, Port1]>] >,
223  InstrItinData<IIC_SSE_SQRTPD_RM, [InstrStage<125, [Port0, Port1]>] >,
224  InstrItinData<IIC_SSE_SQRTSD_RR, [InstrStage<62, [Port0, Port1]>] >,
225  InstrItinData<IIC_SSE_SQRTSD_RM, [InstrStage<62, [Port0, Port1]>] >,
226
227  InstrItinData<IIC_SSE_RSQRTPS_RR, [InstrStage<9, [Port0, Port1]>] >,
228  InstrItinData<IIC_SSE_RSQRTPS_RM, [InstrStage<10, [Port0, Port1]>] >,
229  InstrItinData<IIC_SSE_RSQRTSS_RR, [InstrStage<4, [Port0]>] >,
230  InstrItinData<IIC_SSE_RSQRTSS_RM, [InstrStage<4, [Port0]>] >,
231
232  InstrItinData<IIC_SSE_RCPP_RR, [InstrStage<9, [Port0, Port1]>] >,
233  InstrItinData<IIC_SSE_RCPP_RM, [InstrStage<10, [Port0, Port1]>] >,
234  InstrItinData<IIC_SSE_RCPS_RR, [InstrStage<4, [Port0]>] >,
235  InstrItinData<IIC_SSE_RCPS_RM, [InstrStage<4, [Port0]>] >,
236
237  InstrItinData<IIC_SSE_MOVMSK, [InstrStage<3, [Port0]>] >,
238  InstrItinData<IIC_SSE_MASKMOV, [InstrStage<2, [Port0, Port1]>] >,
239
240  InstrItinData<IIC_SSE_PEXTRW, [InstrStage<4, [Port0, Port1]>] >,
241  InstrItinData<IIC_SSE_PINSRW, [InstrStage<1, [Port0]>] >,
242
243  InstrItinData<IIC_SSE_PABS_RR, [InstrStage<1, [Port0, Port1]>] >,
244  InstrItinData<IIC_SSE_PABS_RM, [InstrStage<1, [Port0]>] >,
245
246  InstrItinData<IIC_SSE_MOV_S_RR, [InstrStage<1, [Port0, Port1]>] >,
247  InstrItinData<IIC_SSE_MOV_S_RM, [InstrStage<1, [Port0]>] >,
248  InstrItinData<IIC_SSE_MOV_S_MR, [InstrStage<1, [Port0]>] >,
249
250  InstrItinData<IIC_SSE_MOVA_P_RR, [InstrStage<1, [Port0, Port1]>] >,
251  InstrItinData<IIC_SSE_MOVA_P_RM, [InstrStage<1, [Port0]>] >,
252  InstrItinData<IIC_SSE_MOVA_P_MR, [InstrStage<1, [Port0]>] >,
253
254  InstrItinData<IIC_SSE_MOVU_P_RR, [InstrStage<1, [Port0, Port1]>] >,
255  InstrItinData<IIC_SSE_MOVU_P_RM, [InstrStage<3, [Port0, Port1]>] >,
256  InstrItinData<IIC_SSE_MOVU_P_MR, [InstrStage<2, [Port0, Port1]>] >,
257
258  InstrItinData<IIC_SSE_MOV_LH, [InstrStage<1, [Port0]>] >,
259
260  InstrItinData<IIC_SSE_LDDQU, [InstrStage<3, [Port0, Port1]>] >,
261
262  InstrItinData<IIC_SSE_MOVDQ, [InstrStage<1, [Port0]>] >,
263  InstrItinData<IIC_SSE_MOVD_ToGP, [InstrStage<3, [Port0]>] >,
264  InstrItinData<IIC_SSE_MOVQ_RR, [InstrStage<1, [Port0, Port1]>] >,
265
266  InstrItinData<IIC_SSE_MOVNT, [InstrStage<1, [Port0]>] >,
267
268  InstrItinData<IIC_SSE_PREFETCH, [InstrStage<1, [Port0]>] >,
269  InstrItinData<IIC_SSE_PAUSE, [InstrStage<17, [Port0, Port1]>] >,
270  InstrItinData<IIC_SSE_LFENCE, [InstrStage<1, [Port0, Port1]>] >,
271  InstrItinData<IIC_SSE_MFENCE, [InstrStage<1, [Port0]>] >,
272  InstrItinData<IIC_SSE_SFENCE, [InstrStage<1, [Port0]>] >,
273  InstrItinData<IIC_SSE_LDMXCSR, [InstrStage<5, [Port0, Port1]>] >,
274  InstrItinData<IIC_SSE_STMXCSR, [InstrStage<15, [Port0, Port1]>] >,
275
276  InstrItinData<IIC_SSE_PHADDSUBD_RR, [InstrStage<3, [Port0, Port1]>] >,
277  InstrItinData<IIC_SSE_PHADDSUBD_RM, [InstrStage<4, [Port0, Port1]>] >,
278  InstrItinData<IIC_SSE_PHADDSUBSW_RR, [InstrStage<7, [Port0, Port1]>] >,
279  InstrItinData<IIC_SSE_PHADDSUBSW_RM, [InstrStage<8, [Port0, Port1]>] >,
280  InstrItinData<IIC_SSE_PHADDSUBW_RR, [InstrStage<7, [Port0, Port1]>] >,
281  InstrItinData<IIC_SSE_PHADDSUBW_RM, [InstrStage<8, [Port0, Port1]>] >,
282  InstrItinData<IIC_SSE_PSHUFB_RR, [InstrStage<4, [Port0, Port1]>] >,
283  InstrItinData<IIC_SSE_PSHUFB_RM, [InstrStage<5, [Port0, Port1]>] >,
284  InstrItinData<IIC_SSE_PSIGN_RR, [InstrStage<1, [Port0, Port1]>] >,
285  InstrItinData<IIC_SSE_PSIGN_RM, [InstrStage<1, [Port0]>] >,
286
287  InstrItinData<IIC_SSE_PMADD, [InstrStage<5, [Port0]>] >,
288  InstrItinData<IIC_SSE_PMULHRSW, [InstrStage<5, [Port0]>] >,
289  InstrItinData<IIC_SSE_PALIGNRR, [InstrStage<1, [Port0]>] >,
290  InstrItinData<IIC_SSE_PALIGNRM, [InstrStage<1, [Port0]>] >,
291  InstrItinData<IIC_SSE_MWAIT, [InstrStage<46, [Port0, Port1]>] >,
292  InstrItinData<IIC_SSE_MONITOR, [InstrStage<45, [Port0, Port1]>] >,
293
294  // conversions
295  // to/from PD ...
296  InstrItinData<IIC_SSE_CVT_PD_RR, [InstrStage<7, [Port0, Port1]>] >,
297  InstrItinData<IIC_SSE_CVT_PD_RM, [InstrStage<8, [Port0, Port1]>] >,
298  // to/from PS except to/from PD and PS2PI
299  InstrItinData<IIC_SSE_CVT_PS_RR, [InstrStage<6, [Port0, Port1]>] >,
300  InstrItinData<IIC_SSE_CVT_PS_RM, [InstrStage<7, [Port0, Port1]>] >,
301  InstrItinData<IIC_SSE_CVT_Scalar_RR, [InstrStage<6, [Port0, Port1]>] >,
302  InstrItinData<IIC_SSE_CVT_Scalar_RM, [InstrStage<7, [Port0, Port1]>] >,
303  InstrItinData<IIC_SSE_CVT_SS2SI32_RR, [InstrStage<8, [Port0, Port1]>] >,
304  InstrItinData<IIC_SSE_CVT_SS2SI32_RM, [InstrStage<9, [Port0, Port1]>] >,
305  InstrItinData<IIC_SSE_CVT_SS2SI64_RR, [InstrStage<9, [Port0, Port1]>] >,
306  InstrItinData<IIC_SSE_CVT_SS2SI64_RM, [InstrStage<10, [Port0, Port1]>] >,
307  InstrItinData<IIC_SSE_CVT_SD2SI_RR, [InstrStage<8, [Port0, Port1]>] >,
308  InstrItinData<IIC_SSE_CVT_SD2SI_RM, [InstrStage<9, [Port0, Port1]>] >,
309
310  // MMX MOVs
311  InstrItinData<IIC_MMX_MOV_MM_RM,  [InstrStage<1, [Port0]>] >,
312  InstrItinData<IIC_MMX_MOV_REG_MM, [InstrStage<3, [Port0]>] >,
313  InstrItinData<IIC_MMX_MOVQ_RM, [InstrStage<1, [Port0]>] >,
314  InstrItinData<IIC_MMX_MOVQ_RR, [InstrStage<1, [Port0, Port1]>] >,
315  // other MMX
316  InstrItinData<IIC_MMX_ALU_RM,  [InstrStage<1, [Port0]>] >,
317  InstrItinData<IIC_MMX_ALU_RR,  [InstrStage<1, [Port0, Port1]>] >,
318  InstrItinData<IIC_MMX_ALUQ_RM, [InstrStage<3, [Port0, Port1]>] >,
319  InstrItinData<IIC_MMX_ALUQ_RR, [InstrStage<2, [Port0, Port1]>] >,
320  InstrItinData<IIC_MMX_PHADDSUBW_RM, [InstrStage<6, [Port0, Port1]>] >,
321  InstrItinData<IIC_MMX_PHADDSUBW_RR, [InstrStage<5, [Port0, Port1]>] >,
322  InstrItinData<IIC_MMX_PHADDSUBD_RM, [InstrStage<4, [Port0, Port1]>] >,
323  InstrItinData<IIC_MMX_PHADDSUBD_RR, [InstrStage<3, [Port0, Port1]>] >,
324  InstrItinData<IIC_MMX_PMUL, [InstrStage<4, [Port0]>] >,
325  InstrItinData<IIC_MMX_MISC_FUNC_MEM, [InstrStage<1, [Port0]>] >,
326  InstrItinData<IIC_MMX_MISC_FUNC_REG, [InstrStage<1, [Port0, Port1]>] >,
327  InstrItinData<IIC_MMX_PSADBW,   [InstrStage<4, [Port0, Port1]>] >,
328  InstrItinData<IIC_MMX_SHIFT_RI, [InstrStage<1, [Port0, Port1]>] >,
329  InstrItinData<IIC_MMX_SHIFT_RM, [InstrStage<3, [Port0, Port1]>] >,
330  InstrItinData<IIC_MMX_SHIFT_RR, [InstrStage<2, [Port0, Port1]>] >,
331  InstrItinData<IIC_MMX_UNPCK_H_RM, [InstrStage<1, [Port0]>] >,
332  InstrItinData<IIC_MMX_UNPCK_H_RR, [InstrStage<1, [Port0, Port1]>] >,
333  InstrItinData<IIC_MMX_UNPCK_L, [InstrStage<1, [Port0]>] >,
334  InstrItinData<IIC_MMX_PCK_RM,  [InstrStage<1, [Port0]>] >,
335  InstrItinData<IIC_MMX_PCK_RR,  [InstrStage<1, [Port0, Port1]>] >,
336  InstrItinData<IIC_MMX_PSHUF,   [InstrStage<1, [Port0]>] >,
337  InstrItinData<IIC_MMX_PEXTR,   [InstrStage<4, [Port0, Port1]>] >,
338  InstrItinData<IIC_MMX_PINSRW,  [InstrStage<1, [Port0]>] >,
339  InstrItinData<IIC_MMX_MASKMOV, [InstrStage<1, [Port0]>] >,
340  // conversions
341  // from/to PD
342  InstrItinData<IIC_MMX_CVT_PD_RR, [InstrStage<7, [Port0, Port1]>] >,
343  InstrItinData<IIC_MMX_CVT_PD_RM, [InstrStage<8, [Port0, Port1]>] >,
344  // from/to PI
345  InstrItinData<IIC_MMX_CVT_PS_RR, [InstrStage<5, [Port1]>] >,
346  InstrItinData<IIC_MMX_CVT_PS_RM, [InstrStage<5, [Port0], 0>,
347                                    InstrStage<5, [Port1]>]>,
348
349  InstrItinData<IIC_CMPX_LOCK, [InstrStage<14, [Port0, Port1]>] >,
350  InstrItinData<IIC_CMPX_LOCK_8, [InstrStage<6, [Port0, Port1]>] >,
351  InstrItinData<IIC_CMPX_LOCK_8B, [InstrStage<18, [Port0, Port1]>] >,
352  InstrItinData<IIC_CMPX_LOCK_16B, [InstrStage<22, [Port0, Port1]>] >,
353
354  InstrItinData<IIC_XADD_LOCK_MEM, [InstrStage<2, [Port0, Port1]>] >,
355  InstrItinData<IIC_XADD_LOCK_MEM, [InstrStage<3, [Port0, Port1]>] >,
356
357  InstrItinData<IIC_FILD, [InstrStage<5, [Port0], 0>, InstrStage<5, [Port1]>] >,
358  InstrItinData<IIC_FLD,  [InstrStage<1, [Port0]>] >,
359  InstrItinData<IIC_FLD80, [InstrStage<4, [Port0, Port1]>] >,
360
361  InstrItinData<IIC_FST,   [InstrStage<2, [Port0, Port1]>] >,
362  InstrItinData<IIC_FST80, [InstrStage<5, [Port0, Port1]>] >,
363  InstrItinData<IIC_FIST,  [InstrStage<6, [Port0, Port1]>] >,
364
365  InstrItinData<IIC_FLDZ,   [InstrStage<1, [Port0, Port1]>] >,
366  InstrItinData<IIC_FUCOM,  [InstrStage<1, [Port1]>] >,
367  InstrItinData<IIC_FUCOMI, [InstrStage<9, [Port0, Port1]>] >,
368  InstrItinData<IIC_FCOMI,  [InstrStage<9, [Port0, Port1]>] >,
369  InstrItinData<IIC_FNSTSW, [InstrStage<10, [Port0, Port1]>] >,
370  InstrItinData<IIC_FNSTCW, [InstrStage<8, [Port0, Port1]>] >,
371  InstrItinData<IIC_FLDCW,  [InstrStage<5, [Port0, Port1]>] >,
372  InstrItinData<IIC_FNINIT, [InstrStage<63, [Port0, Port1]>] >,
373  InstrItinData<IIC_FFREE,  [InstrStage<1, [Port0, Port1]>] >,
374  InstrItinData<IIC_FNCLEX, [InstrStage<25, [Port0, Port1]>] >,
375  InstrItinData<IIC_WAIT,  [InstrStage<1, [Port0, Port1]>] >,
376  InstrItinData<IIC_FXAM,  [InstrStage<1, [Port0]>] >,
377  InstrItinData<IIC_FNOP,  [InstrStage<1, [Port0, Port1]>] >,
378  InstrItinData<IIC_FLDL,  [InstrStage<10, [Port0, Port1]>] >,
379  InstrItinData<IIC_F2XM1,  [InstrStage<99, [Port0, Port1]>] >,
380  InstrItinData<IIC_FYL2X,  [InstrStage<146, [Port0, Port1]>] >,
381  InstrItinData<IIC_FPTAN,  [InstrStage<168, [Port0, Port1]>] >,
382  InstrItinData<IIC_FPATAN,  [InstrStage<183, [Port0, Port1]>] >,
383  InstrItinData<IIC_FXTRACT,  [InstrStage<25, [Port0, Port1]>] >,
384  InstrItinData<IIC_FPREM1,  [InstrStage<71, [Port0, Port1]>] >,
385  InstrItinData<IIC_FPSTP,  [InstrStage<1, [Port0, Port1]>] >,
386  InstrItinData<IIC_FPREM,  [InstrStage<55, [Port0, Port1]>] >,
387  InstrItinData<IIC_FYL2XP1,  [InstrStage<147, [Port0, Port1]>] >,
388  InstrItinData<IIC_FSINCOS,  [InstrStage<174, [Port0, Port1]>] >,
389  InstrItinData<IIC_FRNDINT,  [InstrStage<46, [Port0, Port1]>] >,
390  InstrItinData<IIC_FSCALE,  [InstrStage<77, [Port0, Port1]>] >,
391  InstrItinData<IIC_FCOMPP,  [InstrStage<1, [Port1]>] >,
392  InstrItinData<IIC_FXSAVE,  [InstrStage<140, [Port0, Port1]>] >,
393  InstrItinData<IIC_FXRSTOR,  [InstrStage<141, [Port0, Port1]>] >,
394  InstrItinData<IIC_FXCH, [InstrStage<1, [Port0], 0>, InstrStage<1, [Port1]>] >,
395
396  // System instructions
397  InstrItinData<IIC_CPUID, [InstrStage<121, [Port0, Port1]>] >,
398  InstrItinData<IIC_INT,   [InstrStage<127, [Port0, Port1]>] >,
399  InstrItinData<IIC_INT3,  [InstrStage<130, [Port0, Port1]>] >,
400  InstrItinData<IIC_INVD,  [InstrStage<1003, [Port0, Port1]>] >,
401  InstrItinData<IIC_INVLPG, [InstrStage<71, [Port0, Port1]>] >,
402  InstrItinData<IIC_IRET,  [InstrStage<109, [Port0, Port1]>] >,
403  InstrItinData<IIC_HLT,   [InstrStage<121, [Port0, Port1]>] >,
404  InstrItinData<IIC_LXS,   [InstrStage<10, [Port0, Port1]>] >,
405  InstrItinData<IIC_LTR,   [InstrStage<83, [Port0, Port1]>] >,
406  InstrItinData<IIC_RDTSC, [InstrStage<30, [Port0, Port1]>] >,
407  InstrItinData<IIC_RSM,   [InstrStage<741, [Port0, Port1]>] >,
408  InstrItinData<IIC_SIDT,  [InstrStage<4, [Port0, Port1]>] >,
409  InstrItinData<IIC_SGDT,  [InstrStage<4, [Port0, Port1]>] >,
410  InstrItinData<IIC_SLDT,  [InstrStage<3, [Port0, Port1]>] >,
411  InstrItinData<IIC_STR,    [InstrStage<3, [Port0, Port1]>] >,
412  InstrItinData<IIC_SWAPGS, [InstrStage<22, [Port0, Port1]>] >,
413  InstrItinData<IIC_SYSCALL, [InstrStage<96, [Port0, Port1]>] >,
414  InstrItinData<IIC_SYS_ENTER_EXIT, [InstrStage<88, [Port0, Port1]>] >,
415
416  InstrItinData<IIC_IN_RR,  [InstrStage<94, [Port0, Port1]>] >,
417  InstrItinData<IIC_IN_RI,  [InstrStage<92, [Port0, Port1]>] >,
418  InstrItinData<IIC_OUT_RR, [InstrStage<68, [Port0, Port1]>] >,
419  InstrItinData<IIC_OUT_IR, [InstrStage<72, [Port0, Port1]>] >,
420  InstrItinData<IIC_INS,    [InstrStage<59, [Port0, Port1]>] >,
421
422  InstrItinData<IIC_MOV_REG_DR, [InstrStage<88, [Port0, Port1]>] >,
423  InstrItinData<IIC_MOV_DR_REG, [InstrStage<123, [Port0, Port1]>] >,
424  // worst case for mov REG_CRx
425  InstrItinData<IIC_MOV_REG_CR, [InstrStage<12, [Port0, Port1]>] >,
426  InstrItinData<IIC_MOV_CR_REG, [InstrStage<136, [Port0, Port1]>] >,
427
428  InstrItinData<IIC_MOV_REG_SR, [InstrStage<1, [Port0]>] >,
429  InstrItinData<IIC_MOV_MEM_SR, [InstrStage<2, [Port0, Port1]>] >,
430  InstrItinData<IIC_MOV_SR_REG, [InstrStage<21, [Port0, Port1]>] >,
431  InstrItinData<IIC_MOV_SR_MEM, [InstrStage<26, [Port0, Port1]>] >,
432  // LAR
433  InstrItinData<IIC_LAR_RM,  [InstrStage<50, [Port0, Port1]>] >,
434  InstrItinData<IIC_LAR_RR,  [InstrStage<54, [Port0, Port1]>] >,
435  // LSL
436  InstrItinData<IIC_LSL_RM,  [InstrStage<46, [Port0, Port1]>] >,
437  InstrItinData<IIC_LSL_RR,  [InstrStage<49, [Port0, Port1]>] >,
438
439  InstrItinData<IIC_LGDT, [InstrStage<44, [Port0, Port1]>] >,
440  InstrItinData<IIC_LIDT, [InstrStage<44, [Port0, Port1]>] >,
441  InstrItinData<IIC_LLDT_REG, [InstrStage<60, [Port0, Port1]>] >,
442  InstrItinData<IIC_LLDT_MEM, [InstrStage<64, [Port0, Port1]>] >,
443  // push control register, segment registers
444  InstrItinData<IIC_PUSH_CS, [InstrStage<2, [Port0, Port1]>] >,
445  InstrItinData<IIC_PUSH_SR, [InstrStage<2, [Port0, Port1]>] >,
446  // pop control register, segment registers
447  InstrItinData<IIC_POP_SR,    [InstrStage<29, [Port0, Port1]>] >,
448  InstrItinData<IIC_POP_SR_SS, [InstrStage<48, [Port0, Port1]>] >,
449  // VERR, VERW
450  InstrItinData<IIC_VERR,     [InstrStage<41, [Port0, Port1]>] >,
451  InstrItinData<IIC_VERW_REG, [InstrStage<51, [Port0, Port1]>] >,
452  InstrItinData<IIC_VERW_MEM, [InstrStage<50, [Port0, Port1]>] >,
453  // WRMSR, RDMSR
454  InstrItinData<IIC_WRMSR, [InstrStage<202, [Port0, Port1]>] >,
455  InstrItinData<IIC_RDMSR, [InstrStage<78, [Port0, Port1]>] >,
456  InstrItinData<IIC_RDPMC, [InstrStage<46, [Port0, Port1]>] >,
457  // SMSW, LMSW
458  InstrItinData<IIC_SMSW, [InstrStage<9, [Port0, Port1]>] >,
459  InstrItinData<IIC_LMSW_REG, [InstrStage<69, [Port0, Port1]>] >,
460  InstrItinData<IIC_LMSW_MEM, [InstrStage<67, [Port0, Port1]>] >,
461
462  InstrItinData<IIC_ENTER, [InstrStage<32, [Port0, Port1]>] >,
463  InstrItinData<IIC_LEAVE, [InstrStage<2, [Port0, Port1]>] >,
464
465  InstrItinData<IIC_POP_MEM, [InstrStage<3, [Port0, Port1]>] >,
466  InstrItinData<IIC_POP_REG16, [InstrStage<2, [Port0, Port1]>] >,
467  InstrItinData<IIC_POP_REG, [InstrStage<1, [Port0], 0>,
468                            InstrStage<1, [Port1]>] >,
469  InstrItinData<IIC_POP_F, [InstrStage<32, [Port0, Port1]>] >,
470  InstrItinData<IIC_POP_FD, [InstrStage<26, [Port0, Port1]>] >,
471  InstrItinData<IIC_POP_A, [InstrStage<9, [Port0, Port1]>] >,
472
473  InstrItinData<IIC_PUSH_IMM, [InstrStage<1, [Port0], 0>,
474                               InstrStage<1, [Port1]>] >,
475  InstrItinData<IIC_PUSH_MEM, [InstrStage<2, [Port0, Port1]>] >,
476  InstrItinData<IIC_PUSH_REG, [InstrStage<1, [Port0], 0>,
477                               InstrStage<1, [Port1]>] >,
478  InstrItinData<IIC_PUSH_F, [InstrStage<9, [Port0, Port1]>] >,
479  InstrItinData<IIC_PUSH_A, [InstrStage<8, [Port0, Port1]>] >,
480
481  InstrItinData<IIC_BSWAP, [InstrStage<1, [Port0]>] >,
482  InstrItinData<IIC_BIT_SCAN_MEM, [InstrStage<16, [Port0, Port1]>] >,
483  InstrItinData<IIC_BIT_SCAN_REG, [InstrStage<16, [Port0, Port1]>] >,
484  InstrItinData<IIC_MOVS, [InstrStage<3, [Port0, Port1]>] >,
485  InstrItinData<IIC_STOS, [InstrStage<1, [Port0, Port1]>] >,
486  InstrItinData<IIC_SCAS, [InstrStage<2, [Port0, Port1]>] >,
487  InstrItinData<IIC_CMPS, [InstrStage<3, [Port0, Port1]>] >,
488  InstrItinData<IIC_MOV, [InstrStage<1, [Port0, Port1]>] >,
489  InstrItinData<IIC_MOV_MEM, [InstrStage<1, [Port0]>] >,
490  InstrItinData<IIC_AHF, [InstrStage<1, [Port0, Port1]>] >,
491  InstrItinData<IIC_BT_MI, [InstrStage<1, [Port0, Port1]>] >,
492  InstrItinData<IIC_BT_MR, [InstrStage<9, [Port0, Port1]>] >,
493  InstrItinData<IIC_BT_RI, [InstrStage<1, [Port1]>] >,
494  InstrItinData<IIC_BT_RR, [InstrStage<1, [Port1]>] >,
495  InstrItinData<IIC_BTX_MI, [InstrStage<2, [Port0, Port1]>] >,
496  InstrItinData<IIC_BTX_MR, [InstrStage<11, [Port0, Port1]>] >,
497  InstrItinData<IIC_BTX_RI, [InstrStage<1, [Port1]>] >,
498  InstrItinData<IIC_BTX_RR, [InstrStage<1, [Port1]>] >,
499  InstrItinData<IIC_XCHG_REG, [InstrStage<2, [Port0, Port1]>] >,
500  InstrItinData<IIC_XCHG_MEM, [InstrStage<3, [Port0, Port1]>] >,
501  InstrItinData<IIC_XADD_REG, [InstrStage<2, [Port0, Port1]>] >,
502  InstrItinData<IIC_XADD_MEM, [InstrStage<3, [Port0, Port1]>] >,
503  InstrItinData<IIC_CMPXCHG_MEM, [InstrStage<14, [Port0, Port1]>] >,
504  InstrItinData<IIC_CMPXCHG_REG, [InstrStage<15, [Port0, Port1]>] >,
505  InstrItinData<IIC_CMPXCHG_MEM8, [InstrStage<6, [Port0, Port1]>] >,
506  InstrItinData<IIC_CMPXCHG_REG8, [InstrStage<9, [Port0, Port1]>] >,
507  InstrItinData<IIC_CMPXCHG_8B, [InstrStage<18, [Port0, Port1]>] >,
508  InstrItinData<IIC_CMPXCHG_16B, [InstrStage<22, [Port0, Port1]>] >,
509  InstrItinData<IIC_LODS, [InstrStage<2, [Port0, Port1]>] >,
510  InstrItinData<IIC_OUTS, [InstrStage<74, [Port0, Port1]>] >,
511  InstrItinData<IIC_CLC, [InstrStage<1, [Port0, Port1]>] >,
512  InstrItinData<IIC_CLD, [InstrStage<3, [Port0, Port1]>] >,
513  InstrItinData<IIC_CLI, [InstrStage<14, [Port0, Port1]>] >,
514  InstrItinData<IIC_CMC, [InstrStage<1, [Port0, Port1]>] >,
515  InstrItinData<IIC_CLTS, [InstrStage<33, [Port0, Port1]>] >,
516  InstrItinData<IIC_STC, [InstrStage<1, [Port0, Port1]>] >,
517  InstrItinData<IIC_STI, [InstrStage<17, [Port0, Port1]>] >,
518  InstrItinData<IIC_STD, [InstrStage<21, [Port0, Port1]>] >,
519  InstrItinData<IIC_XLAT, [InstrStage<6, [Port0, Port1]>] >,
520  InstrItinData<IIC_AAA, [InstrStage<13, [Port0, Port1]>] >,
521  InstrItinData<IIC_AAD, [InstrStage<7, [Port0, Port1]>] >,
522  InstrItinData<IIC_AAM, [InstrStage<21, [Port0, Port1]>] >,
523  InstrItinData<IIC_AAS, [InstrStage<13, [Port0, Port1]>] >,
524  InstrItinData<IIC_DAA, [InstrStage<18, [Port0, Port1]>] >,
525  InstrItinData<IIC_DAS, [InstrStage<20, [Port0, Port1]>] >,
526  InstrItinData<IIC_BOUND, [InstrStage<11, [Port0, Port1]>] >,
527  InstrItinData<IIC_ARPL_REG, [InstrStage<24, [Port0, Port1]>] >,
528  InstrItinData<IIC_ARPL_MEM, [InstrStage<23, [Port0, Port1]>] >,
529  InstrItinData<IIC_MOVBE, [InstrStage<1, [Port0]>] >,
530  InstrItinData<IIC_CBW, [InstrStage<4, [Port0, Port1]>] >,
531  InstrItinData<IIC_MMX_EMMS, [InstrStage<5, [Port0, Port1]>] >,
532
533  InstrItinData<IIC_NOP, [InstrStage<1, [Port0, Port1]>] >
534  ]>;
535
536// Atom machine model.
537def AtomModel : SchedMachineModel {
538  let IssueWidth = 2;  // Allows 2 instructions per scheduling group.
539  let MicroOpBufferSize = 0; // In-order execution, always hide latency.
540  let LoadLatency = 3; // Expected cycles, may be overriden by OperandCycles.
541  let HighLatency = 30;// Expected, may be overriden by OperandCycles.
542
543  // On the Atom, the throughput for taken branches is 2 cycles. For small
544  // simple loops, expand by a small factor to hide the backedge cost.
545  let LoopMicroOpBufferSize = 10;
546  let PostRAScheduler = 1;
547  let CompleteModel = 0;
548
549  let Itineraries = AtomItineraries;
550}
551