| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 625 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
627 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
631 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
635 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
1026 : PseudoNLdSt<(outs QPR:$dst),
1027 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1030 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
1031 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1076 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
1100 def : Pat<(vector_insert (v4f32 QPR:$src),
[all …]
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| D | ARMRegisterInfo.td | 313 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16], 128,
316 let AltOrders = [(rotl QPR, 8)];
320 // Subset of QPR that have 32-bit SPR subregs.
322 128, (trunc QPR, 8)>;
324 // Subset of QPR that have DPR_8 and SPR_8 subregs.
326 128, (trunc QPR, 4)>;
339 128, (interleave QPR, TuplesOE2D)> {
342 let AltOrders = [(add (rotl QPR, 8), (rotl DPair, 16))];
371 def Tuples2Q : RegisterTuples<[qsub_0, qsub_1], [(shl QPR, 0), (shl QPR, 1)]>;
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| D | A15SDOptimizer.cpp | 72 bool QPR = false);
429 unsigned Lane, bool QPR) { in createDupLane() argument
430 unsigned Out = MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass : in createDupLane()
435 TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d), in createDupLane()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 181 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
183 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
188 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
190 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
195 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
197 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
544 : PseudoNLdSt<(outs QPR:$dst),
545 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
548 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
549 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
[all …]
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| D | ARMRegisterInfo.td | 297 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
301 let AltOrders = [(rotl QPR, 8)];
305 // Subset of QPR that have 32-bit SPR subregs.
307 128, (trunc QPR, 8)> {
312 // Subset of QPR that have DPR_8 and SPR_8 subregs.
314 128, (trunc QPR, 4)> {
323 (QPR qsub_0, qsub_1)];
342 (QPR qsub_0, qsub_1, qsub_2, qsub_3)];
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| /external/clang/test/CodeGenCXX/ |
| D | nested-base-member-access.cpp | 15 void QPR() { printf("iQ = %d\n", iQ); } in QPR() function
39 this->MPR(); this->PPR(); this->QPR(); in PR()
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| D | constructor-init.cpp | 25 void QPR() {printf("iQ = %d\n", iQ); }; in QPR() function
40 QPR(); in PR()
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| /external/llvm/test/CodeGen/ARM/ |
| D | a15-SD-dep.ll | 60 ; Test that DPair can be successfully passed as QPR.
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| D | coalesce-subregs.ll | 322 ; once under rare circumstances. When widening a register from QPR to DTriple
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| D | vldlane.ll | 503 ; in the QPR_VFP2 regclass, it needs to be copied to a QPR regclass because
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| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| D | vldlane.ll | 491 ; in the QPR_VFP2 regclass, it needs to be copied to a QPR regclass because
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| /external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/de-DE/ |
| D | de-DE_gl0_kpdf_mgc.pkb | 1797 ��������bF��k��� ���+�� ��~������!/"cN3;+>:5\nU#"2J!"*;.=C?)wQ=ZV]Xbat5IKAP\QPR`Yk`T:KjPh_n…
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