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Searched refs:RAX (Results 1 – 25 of 93) sorted by relevance

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/external/llvm/test/CodeGen/X86/
Dabi-isel.ll56 ; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r..]]
57 ; LINUX-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e..]]
85 ; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), [[RAX:%r..]]
86 ; DARWIN-64-STATIC-NEXT: movl ([[RAX]]), [[EAX:%e..]]
92 ; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), [[RAX:%r..]]
93 ; DARWIN-64-DYNAMIC-NEXT: movl ([[RAX]]), [[EAX:%e..]]
99 ; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), [[RAX:%r..]]
100 ; DARWIN-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e..]]
128 ; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
129 ; LINUX-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e.x]]
[all …]
Dpr22103.ll13 ; CHECK: movq %fs:0, [[RAX:%r..]]
14 ; CHECK-NEXT: addq a@GOTTPOFF(%rip), [[RAX]]
15 ; CHECK-NEXT: callq *[[RAX]]
Dhuge-stack-offset.ll12 ; CHECK-64: movabsq $50000000{{..}}, [[RAX:%r..]]
13 ; CHECK-64-NEXT: addq [[RAX]], %rsp
Dobject-size.ll15 ; CHECK: movq $-1, [[RAX:%r..]]
16 ; CHECK: cmpq $-1, [[RAX]]
D2010-02-12-CoalescerBug-Impdef.ll5 ; After coalescing %RAX with a virtual register, this instruction was rematted:
9 ; This instruction silently defined %RAX, and when rematting removed the
10 ; instruction, the live interval for %RAX was not properly updated. The valno
13 ; The fix is to implicitly define %RAX when coalescing:
15 ; %EAX<def> = MOV32rr %reg1070<kill>, %RAX<imp-def>
D2009-09-19-earlyclobber.ll4 ; Registers other than RAX, RCX are OK, but they must be different.
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dabi-isel.ll56 ; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r..]]
57 ; LINUX-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e..]]
85 ; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), [[RAX:%r..]]
86 ; DARWIN-64-STATIC-NEXT: movl ([[RAX]]), [[EAX:%e..]]
92 ; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), [[RAX:%r..]]
93 ; DARWIN-64-DYNAMIC-NEXT: movl ([[RAX]]), [[EAX:%e..]]
99 ; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), [[RAX:%r..]]
100 ; DARWIN-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e..]]
128 ; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
129 ; LINUX-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e.x]]
[all …]
D2010-02-12-CoalescerBug-Impdef.ll5 ; After coalescing %RAX with a virtual register, this instruction was rematted:
9 ; This instruction silently defined %RAX, and when rematting removed the
10 ; instruction, the live interval for %RAX was not properly updated. The valno
13 ; The fix is to implicitly define %RAX when coalescing:
15 ; %EAX<def> = MOV32rr %reg1070<kill>, %RAX<imp-def>
D2009-09-19-earlyclobber.ll4 ; Registers other than RAX, RCX are OK, but they must be different.
/external/llvm/test/MC/X86/
Dintel-syntax.s21 mov RAX, QWORD PTR [RSP]
27 mov EAX, DWORD PTR [RSP + 4*RAX - 24]
67 mov RAX, QWORD PTR FS:[320]
69 mov RAX, QWORD PTR FS:320
71 mov QWORD PTR FS:320, RAX
73 mov QWORD PTR FS:20[rbx], RAX
382 shld [RAX], BX
383 shld [RAX], BX, CL
387 shrd [RAX], BX
388 shrd [RAX], BX, CL
[all …]
Dintel-syntax-encoding.s25 mov QWORD PTR [RSP - 16], RAX
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/X86/
Dintel-syntax.txt30 # CHECK: xchg RAX, R8
42 # CHECK: add RAX, 0
54 # CHECK: adc RAX, 0
66 # CHECK: cmp RAX, 0
78 # CHECK: test RAX, 0
/external/llvm/lib/Target/X86/
DX86InstrSVM.td35 let Uses = [RAX] in
43 let Uses = [RAX] in
51 let Uses = [RAX] in
59 let Uses = [RAX, ECX] in
DX86InstrArithmetic.td78 // RAX,RDX = RAX*GR64
79 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], hasSideEffects = 0 in
82 [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/],
104 // RAX,RDX = RAX*[mem64]
105 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
123 // RAX,RDX = RAX*GR64
124 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
143 // RAX,RDX = RAX*[mem64]
144 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
306 // RDX:RAX/r64 = RAX,RDX
[all …]
DX86InstrExtension.td30 let Defs = [RAX], Uses = [EAX] in
32 "{cltq|cdqe}", [], IIC_CBW>; // RAX = signext(EAX)
34 let Defs = [RAX,RDX], Uses = [RAX] in
36 "{cqto|cqo}", [], IIC_CBW>; // RDX:RAX = signext(RAX)
DX86CallingConv.td41 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
173 // The X86-Win64 calling convention always returns __m64 values in RAX.
186 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>
194 // Return: RAX
195 CCIfType<[i64], CCAssignToReg<[RAX]>>
204 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>,
234 RAX, R10, R11, R13, R14, R15]>>
306 // For Swift Calling Convention, pass sret in %RAX.
308 CCIfSRet<CCIfType<[i64], CCAssignToReg<[RAX]>>>>,
375 RAX, R10, R11, R13, R14]>>
[all …]
/external/strace/linux/x86_64/
Dset_error.c14 return upoke(tcp->pid, 8 * RAX, x86_64_regs.rax); in arch_set_error()
29 return upoke(tcp->pid, 8 * RAX, x86_64_regs.rax); in arch_set_success()
Duserent.h11 XLAT(8*RAX),
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrArithmetic.td65 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
67 "mul{q}\t$src", // RAX,RDX = RAX*GR64
68 [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/]>;
89 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
91 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
104 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
106 // RAX,RDX = RAX*GR64
118 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
120 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
253 // RDX:RAX/r64 = RAX,RDX
[all …]
DX86InstrExtension.td30 let Defs = [RAX], Uses = [EAX] in
32 "{cltq|cdqe}", []>; // RAX = signext(EAX)
34 let Defs = [RAX,RDX], Uses = [RAX] in
36 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
DX86InstrSystem.td16 let Defs = [RAX, RDX] in
19 let Defs = [RAX, RCX, RDX] in
405 let Defs = [RDX, RAX], Uses = [RCX] in
408 let Uses = [RDX, RAX, RCX] in
411 let Uses = [RDX, RAX] in {
428 let Defs = [RAX, RDI], Uses = [RDX, RDI] in
441 let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
445 let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp108 X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::RAX, X86::RBX, in initLLVMToSEHAndCVRegMapping()
293 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
305 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
342 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
378 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
414 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
415 return X86::RAX; in getX86SubSuperRegisterOrZero()
/external/libunwind/src/x86_64/
Dinit.h49 c->dwarf.loc[RAX] = REG_INIT_LOC(c, rax, RAX); in common_init()
Dunwind_i.h39 #define RAX 0 macro
/external/kernel-headers/original/uapi/asm-x86/asm/
Dptrace-abi.h43 #define RAX 80 macro

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