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Searched refs:REG2 (Results 1 – 25 of 170) sorted by relevance

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/external/vulkan-validation-layers/libs/glm/gtx/
Dbit.inl364 glm::uint16 REG2(y); local
367 REG2 = ((REG2 << 4) | REG2) & glm::uint16(0x0F0F);
370 REG2 = ((REG2 << 2) | REG2) & glm::uint16(0x3333);
373 REG2 = ((REG2 << 1) | REG2) & glm::uint16(0x5555);
375 return REG1 | (REG2 << 1);
382 glm::uint32 REG2(y); local
385 REG2 = ((REG2 << 8) | REG2) & glm::uint32(0x00FF00FF);
388 REG2 = ((REG2 << 4) | REG2) & glm::uint32(0x0F0F0F0F);
391 REG2 = ((REG2 << 2) | REG2) & glm::uint32(0x33333333);
394 REG2 = ((REG2 << 1) | REG2) & glm::uint32(0x55555555);
[all …]
/external/llvm/test/CodeGen/AArch64/
Daarch64-be-bv.ll8 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1
9 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
20 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, lsl #8
21 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
32 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, lsl #16
33 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
44 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, lsl #24
45 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
56 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].8h, #1
57 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
[all …]
Dfast-isel-sdiv.ll15 ; CHECK-NEXT: csel [[REG2:w[0-9]+]], [[REG1]], w0, lt
16 ; CHECK-NEXT: asr {{w[0-9]+}}, [[REG2]], #3
25 ; CHECK-NEXT: csel [[REG2:w[0-9]+]], [[REG1]], w0, lt
26 ; CHECK-NEXT: neg {{w[0-9]+}}, [[REG2]], asr #3
42 ; CHECK-NEXT: csel [[REG2:x[0-9]+]], [[REG1]], x0, lt
43 ; CHECK-NEXT: asr {{x[0-9]+}}, [[REG2]], #4
52 ; CHECK-NEXT: csel [[REG2:x[0-9]+]], [[REG1]], x0, lt
53 ; CHECK-NEXT: neg {{x[0-9]+}}, [[REG2]], asr #4
/external/vulkan-validation-layers/libs/glm/detail/
Dintrinsic_integer.inl44 // REG2 = y;
49 //REG2 = ((REG2 << 16) | REG2) & glm::uint64(0x0000FFFF0000FFFF);
55 //REG2 = ((REG2 << 8) | REG2) & glm::uint64(0x00FF00FF00FF00FF);
61 //REG2 = ((REG2 << 4) | REG2) & glm::uint64(0x0F0F0F0F0F0F0F0F);
67 //REG2 = ((REG2 << 2) | REG2) & glm::uint64(0x3333333333333333);
73 //REG2 = ((REG2 << 1) | REG2) & glm::uint64(0x5555555555555555);
78 //return REG1 | (REG2 << 1);
98 // REG2 = y;
102 //REG2 = ((REG2 << 16) | REG2) & glm::uint64(0x0000FFFF0000FFFF);
108 //REG2 = ((REG2 << 8) | REG2) & glm::uint64(0x00FF00FF00FF00FF);
[all …]
/external/llvm/test/CodeGen/ARM/
Datomic-64bit.ll9 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
11 ; CHECK-LE: adc [[REG4:(r[0-9]?[13579])]], [[REG2]]
12 ; CHECK-BE: adds [[REG4:(r[0-9]?[13579])]], [[REG2]]
21 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
23 ; CHECK-THUMB-LE: adc.w [[REG4:[a-z0-9]+]], [[REG2]]
24 ; CHECK-THUMB-BE: adds.w [[REG4:[a-z0-9]+]], [[REG2]]
38 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
40 ; CHECK-LE: sbc [[REG4:(r[0-9]?[13579])]], [[REG2]]
41 ; CHECK-BE: subs [[REG4:(r[0-9]?[13579])]], [[REG2]]
50 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
[all …]
Dgep-optimization.ll12 ; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]]
13 ; CHECK-T1: adds r0, r0, [[REG2]]
23 ; CHECK: mul{{s?}} [[REG2:r[0-9]+]],{{( r1,)?}} [[REG1]]{{(, r1)?}}
24 ; CHECK: ldr r0, [r0, [[REG2]]]
36 ; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]]
37 ; CHECK-T1: adds r0, r0, [[REG2]]
47 ; CHECK: mul{{s?}} [[REG2:r[0-9]+]],{{( r1,)?}} [[REG1]]{{(, r1)?}}
48 ; CHECK: ldr r0, [r0, [[REG2]]]
60 ; CHECK-T1: muls [[REG2:r[0-9]+]], r1, [[REG1]]
61 ; CHECK-T1: adds r0, r0, [[REG2]]
[all …]
/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
Dadv-switch-opt.ll54 ; MIPS32: li [[REG2:.*]],91
55 ; MIPS32: beq [[REG1]],[[REG2]],6c <.LtestJumpTable$sw.default>
57 ; MIPS32: li [[REG2:.*]],92
58 ; MIPS32: beq [[REG1]],[[REG2]],78 <.LtestJumpTable$sw.bb1>
60 ; MIPS32: li [[REG2:.*]],93
61 ; MIPS32: beq [[REG1]],[[REG2]],6c <.LtestJumpTable$sw.default>
63 ; MIPS32: li [[REG2:.*]],99
64 ; MIPS32: beq [[REG1]],[[REG2]],78 <.LtestJumpTable$sw.bb1>
66 ; MIPS32: li [[REG2:.*]],98
67 ; MIPS32: beq [[REG1]],[[REG2]],6c <.LtestJumpTable$sw.default>
[all …]
/external/llvm/test/FileCheck/
Dcheck-dag-xfails.txt16 ; X1-DAG: add [[REG2:r[0-9]+]], r3, r4
17 ; X1: mul r5, [[REG1]], [[REG2]]
28 ; X2-DAG: mul [[REG2:r[0-9]+]], r3, r4
29 ; X2: add r5, [[REG1]], [[REG2]]
40 ; X3-DAG: add [[REG2:r[0-9]+]], r3, r4
41 ; X3-DAG: mul r5, [[REG1]], [[REG2]]
53 ; X4-DAG: add [[REG2:r[0-9]+]], r3, r4
55 ; X4-DAG: mul r5, [[REG1]], [[REG2]]
67 ; X5-DAG: add [[REG2:r[0-9]+]], r3, r4
69 ; X5-DAG: mul r5, [[REG1]], [[REG2]]
[all …]
Dcheck-dag.txt16 ; CHECK-DAG: add [[REG2:r[0-9]+]], r3, r4
17 ; CHECK: mul r5, [[REG1]], [[REG2]]
20 ; CHECK-DAG: mul [[REG2:r[0-9]+]], r3, r4
21 ; CHECK: add r5, [[REG1]], [[REG2]]
24 ; CHECK-DAG: add [[REG2:r[0-9]+]], r3, r4
26 ; CHECK-DAG: mul r5, [[REG1]], [[REG2]]
Dcheck-dag-multi-prefix.txt16 ; B-DAG: add [[REG2:r[0-9]+]], r3, r4
17 ; B: mul r5, [[REG1]], [[REG2]]
20 ; A-DAG: mul [[REG2:r[0-9]+]], r3, r4
21 ; A: add r5, [[REG1]], [[REG2]]
24 ; B-DAG: add [[REG2:r[0-9]+]], r3, r4
26 ; B-DAG: mul r5, [[REG1]], [[REG2]]
/external/llvm/test/CodeGen/X86/
Dlea-opt.ll40 ; CHECK: leaq arr1+4([[REG1]],[[REG1]],2), [[REG2:%[a-z]+]]
44 ; CHECK: movl ${{[1-4]+}}, ([[REG2]])
45 ; ENABLED: movl ${{[1-4]+}}, 4([[REG2]])
47 ; CHECK: movl ${{[1-4]+}}, ([[REG2]])
48 ; ENABLED: movl ${{[1-4]+}}, 4([[REG2]])
82 ; CHECK: leaq arr1+4([[REG1]],[[REG1]],2), [[REG2:%[a-z]+]]
83 ; ENABLED: movl -4([[REG2]]), {{.*}}
84 ; ENABLED: subl ([[REG2]]), {{.*}}
85 ; ENABLED: addl 4([[REG2]]), {{.*}}
89 ; CHECK: movl ${{[1-4]+}}, ([[REG2]])
[all …]
/external/llvm/test/CodeGen/PowerPC/
Danon_aggr.ll33 ; DARWIN32: mr r[[REG2:[0-9]+]], r[[REGB:[0-9]+]]
36 ; DARWIN32: stw r[[REG2]], -[[OFFSET2:[0-9]+]]
43 ; DARWIN64: mr r[[REG2:[0-9]+]], r[[REGB:[0-9]+]]
46 ; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]]
65 ; CHECK: ld [[REG2:[0-9]+]], 72(1)
66 ; CHECK: cmpld {{([0-9]+,)?}}4, [[REG2]]
67 ; CHECK-DAG: std [[REG2]], -[[OFFSET1:[0-9]+]]
74 ; DARWIN32: lwz r[[REG2:[0-9]+]], 44(r[[REGSP]])
77 ; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REGA]], r[[REG2]]
79 ; DARWIN32: stw r[[REG2]], -[[OFFSET2:[0-9]+]]
[all …]
Dbperm.ll26 ; CHECK-DAG: rotldi [[REG2:[0-9]+]], 3, 8
28 ; CHECK-DAG: rldimi [[REG2]], [[REG1]], 8, 48
30 ; CHECK-DAG: rldimi [[REG2]], [[REG3]], 16, 40
32 ; CHECK-DAG: rldimi [[REG2]], [[REG4]], 24, 32
34 ; CHECK-DAG: rldimi [[REG2]], [[REG5]], 40, 16
35 ; CHECK-DAG: rldimi [[REG2]], [[REG6]], 48, 8
36 ; CHECK-DAG: rldimi [[REG2]], 3, 56, 0
37 ; CHECK: mr 3, [[REG2]]
50 ; CHECK-DAG: sldi [[REG2:[0-9]+]], [[REG1]], 19
51 ; CHECK: and 3, [[REG3]], [[REG2]]
[all …]
Dqpx-s-sel.ll28 ; CHECK-DAG: qvlfdx [[REG2:[0-9]+]],
30 ; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]]
56 ; CHECK-DAG: qvlfiwzx [[REG2:[0-9]+]],
57 ; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]]
70 ; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
71 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
85 ; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
86 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
101 ; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
102 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
[all …]
Dtls.ll14 ;OPT0-NEXT: li [[REG2:[0-9]+]], 42
16 ;OPT0: stw [[REG2]], 0([[REG1]])
18 ;OPT1-NEXT: li [[REG2:[0-9]+]], 42
19 ;OPT1-NEXT: stw [[REG2]], a@tprel@l([[REG1]])
39 ; OPT1: ld [[REG2:[0-9]+]], a2@got@tprel@l([[REG1]])
40 ; OPT1: add {{[0-9]+}}, [[REG2]], a2@tls
45 ;OPT0-PPC32: lwz [[REG2:[0-9]+]], a2@got@tprel@l([[REG1]])
46 ;OPT0-PPC32: add 3, [[REG2]], a2@tls
Dqpx-sel.ll32 ; CHECK-DAG: qvlfdx [[REG2:[0-9]+]],
34 ; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]]
60 ; CHECK-DAG: qvlfiwzx [[REG2:[0-9]+]],
61 ; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]]
74 ; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
75 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
89 ; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
90 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
105 ; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
106 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
[all …]
Dmcm-4.ll21 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
22 ; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]])
28 ; MEDIUM-VSX: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
29 ; MEDIUM-VSX: lxsdx {{[0-9]+}}, 0, [[REG2]]
35 ; LARGE: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
36 ; LARGE: lfd {{[0-9]+}}, 0([[REG2]])
42 ; LARGE-VSX: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
43 ; LARGE-VSX: lxsdx {{[0-9]+}}, 0, [[REG2]]
Dunal-vec-ldst.ll12 ; CHECK-DAG: lvsl [[REG2:[0-9]+]], 0, 3
15 ; CHECK: vperm 2, [[REG4]], [[REG3]], [[REG2]]
26 ; CHECK-DAG: li [[REG2:[0-9]+]], 16
29 ; CHECK-DAG: lvx [[REG5:[0-9]+]], 3, [[REG2]]
43 ; CHECK-DAG: lvsl [[REG2:[0-9]+]], 0, 3
46 ; CHECK: vperm 2, [[REG4]], [[REG3]], [[REG2]]
57 ; CHECK-DAG: li [[REG2:[0-9]+]], 16
60 ; CHECK-DAG: lvx [[REG5:[0-9]+]], 3, [[REG2]]
74 ; CHECK-DAG: lvsl [[REG2:[0-9]+]], 0, 3
77 ; CHECK: vperm 2, [[REG4]], [[REG3]], [[REG2]]
[all …]
Dvaddsplat.ll86 ; CHECK: vspltisw [[REG2:[0-9]+]], -16
88 ; CHECK: vsubuwm {{[0-9]+}}, [[REG1]], [[REG2]]
98 ; CHECK: vspltisw [[REG2:[0-9]+]], -16
100 ; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG2]]
110 ; CHECK: vspltish [[REG2:[0-9]+]], -16
112 ; CHECK: vsubuhm {{[0-9]+}}, [[REG1]], [[REG2]]
122 ; CHECK: vspltish [[REG2:[0-9]+]], -16
124 ; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG2]]
134 ; CHECK: vspltisb [[REG2:[0-9]+]], -16
136 ; CHECK: vsububm {{[0-9]+}}, [[REG1]], [[REG2]]
[all …]
Dno-extra-fp-conv-ldst.ll39 ; CHECK-DAG: fctiwz [[REG2:[0-9]+]], 1
41 ; CHECK: stfiwx [[REG2]], 0, [[REG1]]
55 ; CHECK-DAG: fctiwz [[REG2:[0-9]+]], 1
57 ; CHECK: stfiwx [[REG2]], 0, [[REG1]]
71 ; CHECK-DAG: fctiwuz [[REG2:[0-9]+]], 1
73 ; CHECK: stfiwx [[REG2]], 0, [[REG1]]
87 ; CHECK-DAG: fctiwuz [[REG2:[0-9]+]], 1
89 ; CHECK: stfiwx [[REG2]], 0, [[REG1]]
Dmcm-3.ll22 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
23 ; MEDIUM: lwz {{[0-9]+}}, 0([[REG2]])
24 ; MEDIUM: stw {{[0-9]+}}, 0([[REG2]])
33 ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
34 ; LARGE: lwz {{[0-9]+}}, 0([[REG2]])
35 ; LARGE: stw {{[0-9]+}}, 0([[REG2]])
Dmcm-2.ll22 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
23 ; MEDIUM: lwz {{[0-9]+}}, 0([[REG2]])
24 ; MEDIUM: stw {{[0-9]+}}, 0([[REG2]])
30 ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
31 ; LARGE: lwz {{[0-9]+}}, 0([[REG2]])
32 ; LARGE: stw {{[0-9]+}}, 0([[REG2]])
/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dsimplestorei.ll14 ; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
15 ; CHECK: sw $[[REG1]], 0($[[REG2]])
26 ; CHECK: ori $[[REG2:[0-9]+]], $[[REG1]], 32768
28 ; CHECK: sw $[[REG2]], 0($[[REG3]])
38 ; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
39 ; CHECK: sw $[[REG1]], 0($[[REG2]])
49 ; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
50 ; CHECK: sw $[[REG1]], 0($[[REG2]])
61 ; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
62 ; CHECK: sw $[[REG1]], 0($[[REG2]])
/external/llvm/test/CodeGen/SystemZ/
Dstack-guard.ll10 ; CHECK: ear [[REG2:%r[1-9][0-9]?]], %a0
11 ; CHECK: sllg [[REG2]], [[REG2]], 32
12 ; CHECK: ear [[REG2]], %a1
13 ; CHECK: lg [[REG2]], 40([[REG2]])
14 ; CHECK: sg [[REG2]], {{[0-9]*}}(%r15)
Dasm-18.ll11 ; CHECK-DAG: l [[REG2:%r[0-5]]], 0(%r3)
14 ; CHECK: blah [[REG1]], [[REG2]], [[REG3]], [[REG4]]
16 ; CHECK-DAG: st [[REG2]], 0(%r3)
46 ; CHECK: stepb [[REG2:%r[0-5]]]
47 ; CHECK: risblg %r2, [[REG2]], 0, 159, 32
59 ; CHECK-DAG: lb [[REG2:%r[0-5]]], 0(%r3)
62 ; CHECK: blah [[REG1]], [[REG2]]
83 ; CHECK-DAG: lh [[REG2:%r[0-5]]], 0(%r3)
86 ; CHECK: blah [[REG1]], [[REG2]]
107 ; CHECK-DAG: llc [[REG2:%r[0-5]]], 0(%r3)
[all …]

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