1; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s 2target triple = "powerpc64-bgq-linux" 3 4@R = global <4 x i1> <i1 0, i1 0, i1 0, i1 0>, align 16 5 6define <4 x double> @test1(<4 x double> %a, <4 x double> %b, <4 x i1> %c) nounwind readnone { 7entry: 8 %r = select <4 x i1> %c, <4 x double> %a, <4 x double> %b 9 ret <4 x double> %r 10 11; CHECK-LABEL: @test1 12; CHECK: qvfsel 1, 3, 1, 2 13; CHECK: blr 14} 15 16define <4 x double> @test2(<4 x double> %a, <4 x double> %b, i1 %c1, i1 %c2, i1 %c3, i1 %c4) nounwind readnone { 17entry: 18 %v = insertelement <4 x i1> undef, i1 %c1, i32 0 19 %v2 = insertelement <4 x i1> %v, i1 %c2, i32 1 20 %v3 = insertelement <4 x i1> %v2, i1 %c3, i32 2 21 %v4 = insertelement <4 x i1> %v3, i1 %c4, i32 3 22 %r = select <4 x i1> %v4, <4 x double> %a, <4 x double> %b 23 ret <4 x double> %r 24 25; CHECK-LABEL: @test2 26 27; FIXME: This load/store sequence is unnecessary. 28; CHECK-DAG: lbz 29; CHECK-DAG: stw 30 31; CHECK-DAG: qvlfiwzx [[REG1:[0-9]+]], 32; CHECK-DAG: qvlfdx [[REG2:[0-9]+]], 33; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG1]] 34; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]] 35; CHECK: qvfsel 1, [[REG4]], 1, 2 36; CHECK: blr 37} 38 39define <4 x i1> @test3(<4 x i1> %a) nounwind readnone { 40entry: 41 %v = and <4 x i1> %a, <i1 0, i1 undef, i1 1, i1 1> 42 ret <4 x i1> %v 43 44; CHECK-LABEL: @test3 45; CHECK: qvlfsx [[REG:[0-9]+]], 46; qvflogical 1, 1, [[REG]], 1 47; blr 48} 49 50define <4 x i1> @test4(<4 x i1> %a, <4 x i1>* %t) nounwind { 51entry: 52 %q = load <4 x i1>, <4 x i1>* %t, align 16 53 %v = and <4 x i1> %a, %q 54 ret <4 x i1> %v 55 56; CHECK-LABEL: @test4 57; CHECK-DAG: lbz 58; CHECK-DAG: qvlfdx [[REG1:[0-9]+]], 59; CHECK-DAG: stw 60; CHECK-DAG: qvlfiwzx [[REG2:[0-9]+]], 61; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]] 62; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG1]] 63; CHECK: qvflogical 1, 1, [[REG4]], 1 64; CHECK: blr 65} 66 67define void @test5(<4 x i1> %a) nounwind { 68entry: 69 store <4 x i1> %a, <4 x i1>* @R 70 ret void 71 72; CHECK-LABEL: @test5 73; CHECK: qvlfdx [[REG1:[0-9]+]], 74; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]] 75; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]] 76; CHECK: qvstfiwx [[REG3]], 77; CHECK: lwz 78; CHECK: stb 79; CHECK: blr 80} 81 82define i1 @test6(<4 x i1> %a) nounwind { 83entry: 84 %r = extractelement <4 x i1> %a, i32 2 85 ret i1 %r 86 87; CHECK-LABEL: @test6 88; CHECK: qvlfdx [[REG1:[0-9]+]], 89; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]] 90; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]] 91; CHECK: qvstfiwx [[REG3]], 92; CHECK: lwz 93; CHECK: blr 94} 95 96define i1 @test7(<4 x i1> %a) nounwind { 97entry: 98 %r = extractelement <4 x i1> %a, i32 2 99 %s = extractelement <4 x i1> %a, i32 3 100 %q = and i1 %r, %s 101 ret i1 %q 102 103; CHECK-LABEL: @test7 104; CHECK: qvlfdx [[REG1:[0-9]+]], 105; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]] 106; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]] 107; CHECK: qvstfiwx [[REG3]], 108; CHECK-DAG: lwz [[REG4:[0-9]+]], 109; FIXME: We're storing the vector twice, and that's silly. 110; CHECK-DAG: qvstfiwx [[REG3]], 111; CHECK-DAG: lwz [[REG5:[0-9]+]], 112; CHECK: and 3, 113; CHECK: blr 114} 115 116define i1 @test8(<3 x i1> %a) nounwind { 117entry: 118 %r = extractelement <3 x i1> %a, i32 2 119 ret i1 %r 120 121; CHECK-LABEL: @test8 122; CHECK: qvlfdx [[REG1:[0-9]+]], 123; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]] 124; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]] 125; CHECK: qvstfiwx [[REG3]], 126; CHECK: lwz 127; CHECK: blr 128} 129 130define <3 x double> @test9(<3 x double> %a, <3 x double> %b, i1 %c1, i1 %c2, i1 %c3) nounwind readnone { 131entry: 132 %v = insertelement <3 x i1> undef, i1 %c1, i32 0 133 %v2 = insertelement <3 x i1> %v, i1 %c2, i32 1 134 %v3 = insertelement <3 x i1> %v2, i1 %c3, i32 2 135 %r = select <3 x i1> %v3, <3 x double> %a, <3 x double> %b 136 ret <3 x double> %r 137 138; CHECK-LABEL: @test9 139 140; FIXME: This load/store sequence is unnecessary. 141; CHECK-DAG: lbz 142; CHECK-DAG: stw 143 144; CHECK-DAG: qvlfiwzx [[REG1:[0-9]+]], 145; CHECK-DAG: qvlfdx [[REG2:[0-9]+]], 146; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG1]] 147; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]] 148; CHECK: qvfsel 1, [[REG4]], 1, 2 149; CHECK: blr 150} 151 152