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Searched refs:REG3 (Results 1 – 25 of 70) sorted by relevance

123

/external/vulkan-validation-layers/libs/glm/gtx/
Dbit.inl428 glm::uint32 REG3(z); local
432 REG3 = ((REG3 << 16) | REG3) & glm::uint32(0x00FF0000FF0000FF);
436 REG3 = ((REG3 << 8) | REG3) & glm::uint32(0xF00F00F00F00F00F);
440 REG3 = ((REG3 << 4) | REG3) & glm::uint32(0x30C30C30C30C30C3);
444 REG3 = ((REG3 << 2) | REG3) & glm::uint32(0x9249249249249249);
446 return REG1 | (REG2 << 1) | (REG3 << 2);
454 glm::uint64 REG3(z); local
458 REG3 = ((REG3 << 32) | REG3) & glm::uint64(0xFFFF00000000FFFF);
462 REG3 = ((REG3 << 16) | REG3) & glm::uint64(0x00FF0000FF0000FF);
466 REG3 = ((REG3 << 8) | REG3) & glm::uint64(0xF00F00F00F00F00F);
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dppc64-nonfunc-calls.ll20 ; CHECK-DAG: addi [[REG3:[0-9]+]], [[REG1]], something@toc@l
21 ; CHECK-DAG: ld [[REG2:[0-9]+]], 0([[REG3]])
22 ; CHECK-DAG: ld 11, 16([[REG3]])
23 ; CHECK-DAG: ld 2, 8([[REG3]])
39 ; CHECK-DAG: addi [[REG3:[0-9]+]], [[REG1]], tls_something@tprel@l
40 ; CHECK-DAG: ld [[REG2:[0-9]+]], 0([[REG3]])
41 ; CHECK-DAG: ld 11, 16([[REG3]])
42 ; CHECK-DAG: ld 2, 8([[REG3]])
58 ; CHECK-DAG: ld [[REG3:[0-9]+]], [[NAME]]@toc@l(3)
59 ; CHECK-DAG: ld [[REG2:[0-9]+]], 0([[REG3]])
[all …]
Danon_aggr.ll76 ; DARWIN32: mr r[[REG3:[0-9]+]], r[[REGA:[0-9]+]]
78 ; DARWIN32: stw r[[REG3]], -[[OFFSET1:[0-9]+]]
86 ; DARWIN64: mr r[[REG3:[0-9]+]], r[[REGA:[0-9]+]]
88 ; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]]
109 ; CHECK: ld [[REG3:[0-9]+]], 72(1)
111 ; CHECK: cmpld {{([0-9]+,)?}}[[REG4]], [[REG3]]
112 ; CHECK: std [[REG3]], -[[OFFSET1:[0-9]+]](1)
120 ; DARWIN32: lwz r[[REG3:[0-9]+]], 44(r[[REGSP]])
122 ; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REG4]], r[[REG3]]
123 ; DARWIN32: stw r[[REG3]], -[[OFFSET1:[0-9]+]]
[all …]
Dqpx-s-sel.ll29 ; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG1]]
30 ; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]]
57 ; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]]
58 ; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG1]]
71 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
72 ; CHECK: qvstfiwx [[REG3]],
86 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
87 ; CHECK: qvstfiwx [[REG3]],
102 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
103 ; CHECK: qvstfiwx [[REG3]],
[all …]
Dqpx-sel.ll33 ; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG1]]
34 ; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]]
61 ; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]]
62 ; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG1]]
75 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
76 ; CHECK: qvstfiwx [[REG3]],
90 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
91 ; CHECK: qvstfiwx [[REG3]],
106 ; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
107 ; CHECK: qvstfiwx [[REG3]],
[all …]
Dunal-vec-ldst.ll13 ; CHECK-DAG: lvx [[REG3:[0-9]+]], 3, [[REG1]]
15 ; CHECK: vperm 2, [[REG4]], [[REG3]], [[REG2]]
27 ; CHECK-DAG: lvsl [[REG3:[0-9]+]], 0, 3
31 ; CHECK-DAG: vperm 3, [[REG5]], [[REG4]], [[REG3]]
32 ; CHECK-DAG: vperm 2, [[REG6]], [[REG5]], [[REG3]]
44 ; CHECK-DAG: lvx [[REG3:[0-9]+]], 3, [[REG1]]
46 ; CHECK: vperm 2, [[REG4]], [[REG3]], [[REG2]]
58 ; CHECK-DAG: lvsl [[REG3:[0-9]+]], 0, 3
62 ; CHECK-DAG: vperm 3, [[REG5]], [[REG4]], [[REG3]]
63 ; CHECK-DAG: vperm 2, [[REG6]], [[REG5]], [[REG3]]
[all …]
Dbperm.ll27 ; CHECK-DAG: rotldi [[REG3:[0-9]+]], 3, 24
30 ; CHECK-DAG: rldimi [[REG2]], [[REG3]], 16, 40
49 ; CHECK-DAG: rotldi [[REG3:[0-9]+]], 4, 56
51 ; CHECK: and 3, [[REG3]], [[REG2]]
65 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 32
66 ; CHECK-DAG: oris [[REG4:[0-9]+]], [[REG3]], 25464
81 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 34
82 ; CHECK: and 3, [[REG4]], [[REG3]]
108 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 19
109 ; CHECK: and 3, [[REG4]], [[REG3]]
[all …]
Dno-extra-fp-conv-ldst.ll42 ; CHECK: lfiwax [[REG3:[0-9]+]], 0, [[REG1]]
43 ; CHECK: fcfids 1, [[REG3]]
58 ; CHECK: lfiwax [[REG3:[0-9]+]], 0, [[REG1]]
59 ; CHECK: fcfid 1, [[REG3]]
74 ; CHECK: lfiwzx [[REG3:[0-9]+]], 0, [[REG1]]
75 ; CHECK: fcfidus 1, [[REG3]]
90 ; CHECK: lfiwzx [[REG3:[0-9]+]], 0, [[REG1]]
91 ; CHECK: fcfidu 1, [[REG3]]
Dcrbit-asm.ll18 ; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
20 ; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
37 ; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
39 ; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
53 ; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
55 ; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
Dppc-crbits-onoff.ll17 ; CHECK-DAG: cntlzw [[REG3:[0-9]+]],
19 ; CHECK: and 3, [[REG4]], [[REG3]]
35 ; CHECK-DAG: crorc [[REG3:[0-9]+]],
36 ; CHECK: isel 3, 0, [[REG2]], [[REG3]]
Dqpx-bv.ll16 ; CHECK-DAG: qvfperm [[REG3:[0-9]+]], 3, 4, [[REG1]]
18 ; CHECK-DAG: qvfperm 1, [[REG4]], [[REG3]], [[REG2]]
32 ; CHECK-DAG: qvfperm [[REG3:[0-9]+]], 3, 4, [[REG1]]
34 ; CHECK-DAG: qvfperm 1, [[REG4]], [[REG3]], [[REG2]]
Dfp-to-int-ext.ll42 ; CHECK-DAG: addi [[REG3:[0-9]+]], 1,
45 ; CHECK: lfiwzx [[REG4:[0-9]+]], 0, [[REG3]]
60 ; CHECK-DAG: addi [[REG3:[0-9]+]], 1,
63 ; CHECK: lfiwax [[REG4:[0-9]+]], 0, [[REG3]]
Dcc.ll28 ; CHECK: lwz [[REG3:[0-9]+]], -4(1)
29 ; CHECK: mtocrf 128, [[REG3]]
61 ; CHECK: lwz [[REG3:[0-9]+]], -4(1)
62 ; CHECK: mtocrf 128, [[REG3]]
Dswaps-le-5.ll20 ; CHECK: xxpermdi [[REG3:[0-9]+]], [[REG2]], [[REG1]], 1
21 ; CHECK: stxvd2x [[REG3]]
35 ; CHECK: xxmrghd [[REG3:[0-9]+]], [[REG1]], [[REG2]]
36 ; CHECK: stxvd2x [[REG3]]
Dvec_shuffle_le.ll11 ; CHECK: vpkuhum [[REG3:[0-9]+]], [[REG2]], [[REG1]]
34 ; CHECK: vpkuwum [[REG3:[0-9]+]], [[REG2]], [[REG1]]
57 ; CHECK: vmrglb [[REG3:[0-9]+]], [[REG2]], [[REG1]]
80 ; CHECK: vmrghb [[REG3:[0-9]+]], [[REG2]], [[REG1]]
103 ; CHECK: vmrglh [[REG3:[0-9]+]], [[REG2]], [[REG1]]
126 ; CHECK: vmrghh [[REG3:[0-9]+]], [[REG2]], [[REG1]]
149 ; CHECK: vmrglw [[REG3:[0-9]+]], [[REG2]], [[REG1]]
172 ; CHECK: vmrghw [[REG3:[0-9]+]], [[REG2]], [[REG1]]
195 ; CHECK: vsldoi [[REG3:[0-9]+]], [[REG2]], [[REG1]], 4
Dppc32-vacopy.ll21 ; CHECK: lwz [[REG3:[0-9]+]], {{.*}}
24 ; CHECK: stw [[REG3]], {{.*}}
/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dsimplestorefp1.ll21 ; CHECK: mtc1 $[[REG2]], $f[[REG3:[0-9]+]]
23 ; CHECK: swc1 $f[[REG3]], 0($[[REG4]])
37 ; mips32r2: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]]
38 ; mips32r2: mthc1 $[[REG2a]], $f[[REG3]]
39 ; mips32r2: sdc1 $f[[REG3]], 0(${{[0-9]+}})
46 ; mips32: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]]
48 ; mips32: sdc1 $f[[REG3]], 0(${{[0-9]+}})
/external/llvm/test/CodeGen/ARM/
Datomic-64bit.ll10 ; CHECK-LE: adds [[REG3:(r[0-9]?[02468])]], [[REG1]]
13 ; CHECK-BE: adc [[REG3:(r[0-9]?[02468])]], [[REG1]]
14 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
22 ; CHECK-THUMB-LE: adds.w [[REG3:[a-z0-9]+]], [[REG1]]
25 ; CHECK-THUMB-BE: adc.w [[REG3:[a-z0-9]+]], [[REG1]]
26 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
39 ; CHECK-LE: subs [[REG3:(r[0-9]?[02468])]], [[REG1]]
42 ; CHECK-BE: sbc [[REG3:(r[0-9]?[02468])]], [[REG1]]
43 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
51 ; CHECK-THUMB-LE: subs.w [[REG3:[a-z0-9]+]], [[REG1]]
[all …]
Dfcopysign.ll35 ; SOFT: vmov.i32 [[REG3:(d[0-9]+)]], #0x80000000
36 ; SOFT: vshl.i64 [[REG3]], [[REG3]], #32
37 ; SOFT: vbsl [[REG3]],
/external/llvm/test/CodeGen/X86/
Dlea-opt.ll42 ; DISABLED: leaq arr1+8([[REG1]],[[REG1]],2), [[REG3:%[a-z]+]]
46 ; DISABLED: movl ${{[1-4]+}}, ([[REG3]])
49 ; DISABLED: movl ${{[1-4]+}}, ([[REG3]])
87 ; DISABLED: leaq arr1+8([[REG1]],[[REG1]],2), [[REG3:%[a-z]+]]
91 ; DISABLED: movl ${{[1-4]+}}, ([[REG3]])
94 ; DISABLED: movl ${{[1-4]+}}, ([[REG3]])
120 ; Make sure the REG3's definition LEA won't be removed as redundant.
130 ; CHECK: leaq arr2([[REG1]]), [[REG3:%[a-z]+]]
132 ; REG3's definition is closer to movl than REG2's, but the pass still chooses
136 ; ENABLED: addl ([[REG3]]), {{.*}}
[all …]
Dhalf.ll130 ; CHECK-LIBCALL-NEXT: cvttss2si [[REG2]], [[REG3:%[a-z0-9]+]]
132 ; CHECK-LIBCALL-NEXT: xorq [[REG3]], [[REG4]]
142 ; CHECK-F16C-NEXT: vmovss {{.[A-Z_0-9]+}}(%rip), [[REG3:%[a-z0-9]+]]
143 ; CHECK-F16C-NEXT: vsubss [[REG3]], [[REG2]], [[REG4:%[a-z0-9]+]]
148 ; CHECK-F16C-NEXT: vucomiss [[REG3]], [[REG2]]
174 ; CHECK-LIBCALL-NEXT: cvtsi2ssq [[REG2]], [[REG3:%[a-z0-9]+]]
175 ; CHECK-LIBCALL-NEXT: addss [[REG3]], [[REG1]]
176 ; CHECK-F16C-NEXT: vcvtsi2ssq [[REG2]], [[REG3:%[a-z0-9]+]], [[REG3]]
177 ; CHECK-F16C-NEXT: vaddss [[REG3]], [[REG3]], [[REG1:[%a-z0-9]+]]
Dmmx-fold-load.ll142 ; CHECK: paddb (%[[REG3:[a-z]+]]), %mm0
159 ; CHECK: paddw (%[[REG3]]), %mm0
175 ; CHECK: paddd (%[[REG3]]), %mm0
191 ; CHECK: paddq (%[[REG3]]), %mm0
207 ; CHECK: paddusb (%[[REG3]]), %mm0
223 ; CHECK: paddusw (%[[REG3]]), %mm0
239 ; CHECK: psrlw (%[[REG3]]), %mm0
255 ; CHECK: psrld (%[[REG3]]), %mm0
271 ; CHECK: psrlq (%[[REG3]]), %mm0
/external/llvm/test/CodeGen/AArch64/
Darm64-fast-isel-addr-offset.ll13 ; CHECK: add x[[REG3:[0-9]+]], x[[REG1]], x[[REG2]]
14 ; CHECK: ldr w0, [x[[REG3]]]
26 ; CHECK: add x[[REG3:[0-9]+]], x[[REG1]], x[[REG2]]
27 ; CHECK: ldr x0, [x[[REG3]]]
/external/llvm/test/CodeGen/SystemZ/
Dasm-18.ll12 ; CHECK-DAG: lfh [[REG3:%r[0-5]]], 4096(%r2)
14 ; CHECK: blah [[REG1]], [[REG2]], [[REG3]], [[REG4]]
17 ; CHECK-DAG: stfh [[REG3]], 4096(%r2)
60 ; CHECK-DAG: lbh [[REG3:%r[0-5]]], 4096(%r2)
84 ; CHECK-DAG: lhh [[REG3:%r[0-5]]], 4096(%r2)
108 ; CHECK-DAG: llch [[REG3:%r[0-5]]], 4096(%r2)
132 ; CHECK-DAG: llhh [[REG3:%r[0-5]]], 4096(%r2)
203 ; CHECK: risbhg [[REG3:%r[0-5]]], [[REG1]], 24, 159, 0
204 ; CHECK: stepb [[REG3]]
205 ; CHECK: risblg %r2, [[REG3]], 24, 159, 32
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dfcopysign.ll35 ; SOFT: vmov.i32 [[REG3:(d[0-9]+)]], #0x80000000
36 ; SOFT: vshl.i64 [[REG3]], [[REG3]], #32
37 ; SOFT: vbsl [[REG3]],

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