/external/llvm/test/CodeGen/AMDGPU/ |
D | detect-dead-lanes.mir | 19 # CHECK: %3 = REG_SEQUENCE %0, {{[0-9]+}}, %1, {{[0-9]+}}, undef %2, {{[0-9]+}} 42 %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub3 56 # CHECK: %0 = REG_SEQUENCE %sgpr0, {{[0-9]+}}, %sgpr0, {{[0-9]+}} 102 %0 = REG_SEQUENCE %sgpr0, %subreg.sub0, %sgpr0, %subreg.sub2 140 # CHECK: %3 = REG_SEQUENCE undef %0, {{[0-9]+}}, %1, {{[0-9]+}}, %2, {{[0-9]+}} 146 # CHECK: %6 = REG_SEQUENCE %4, {{[0-9]+}}, undef %5, {{[0-9]+}} 161 # CHECK: %15 = REG_SEQUENCE %13, {{[0-9]+}}, undef %14, {{[0-9]+}} 190 %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2_sub3 196 %6 = REG_SEQUENCE %4, %subreg.sub0, undef %5, %subreg.sub1 211 %15 = REG_SEQUENCE %13, %subreg.sub0_sub1, %14, %subreg.sub2_sub3 [all …]
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D | sgpr-copy-duplicate-operand.ll | 5 ; used in an REG_SEQUENCE that also needs to be handled.
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D | literals.ll | 37 ; Make sure inline literals are folded into REG_SEQUENCE instructions.
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D | si-lod-bias.ll | 5 ; the wrong register class is used for the REG_SEQUENCE instructions.
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/external/llvm/test/CodeGen/MIR/X86/ |
D | subregister-index-operands.mir | 17 # CHECK: %ax = REG_SEQUENCE %1, {{[0-9]+}}, %1, {{[0-9]+}} 29 %ax = REG_SEQUENCE %1, %subreg.sub_8bit, %1, %subreg.sub_8bit_hi
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/external/swiftshader/third_party/LLVM/include/llvm/Target/ |
D | TargetOpcodes.h | 81 REG_SEQUENCE = 12, enumerator
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/external/llvm/lib/CodeGen/ |
D | DetectDeadLanes.cpp | 148 case TargetOpcode::REG_SEQUENCE: in lowersToCopies() 174 case TargetOpcode::REG_SEQUENCE: { in isCrossCopy() 243 case TargetOpcode::REG_SEQUENCE: { in transferUsedLanes() 318 case TargetOpcode::REG_SEQUENCE: { in transferDefinedLanes()
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/external/llvm/include/llvm/Target/ |
D | TargetOpcodes.def | 75 /// REG_SEQUENCE - This variadic instruction is used to form a register that 80 // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index 83 /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5 86 HANDLE_TARGET_OPCODE(REG_SEQUENCE, 12)
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/external/llvm/test/CodeGen/ARM/ |
D | 2012-01-24-RegSequenceLiveRange.ll | 7 ; This test case is exercising REG_SEQUENCE, and chains of REG_SEQUENCE.
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D | crash.ll | 31 ; PR10520 - REG_SEQUENCE with implicit-def operands.
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/external/llvm/lib/Target/AMDGPU/ |
D | SIInstrInfo.cpp | 1787 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE; in getVALUOp() 1867 case AMDGPU::REG_SEQUENCE: in canReadVGPR() 2184 get(AMDGPU::REG_SEQUENCE), DstReg); in readlaneVGPRToSGPR() 2278 if (MI.getOpcode() == AMDGPU::REG_SEQUENCE) { in legalizeOperands() 2383 BuildMI(MBB, MI, MI.getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewSRsrc) in legalizeOperands() 2411 BuildMI(MBB, MI, MI.getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr) in legalizeOperands() 2478 BuildMI(MBB, Addr64, Addr64->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), in legalizeOperands() 2734 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg) in splitScalar64BitUnaryOp() 2799 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg) in splitScalar64BitBinaryOp() 2889 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg) in splitScalar64BitBFE() [all …]
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D | R600OptimizeVectorRegisters.cpp | 69 assert(MI->getOpcode() == AMDGPU::REG_SEQUENCE); in RegSeqInfo() 335 if (MI.getOpcode() != AMDGPU::REG_SEQUENCE) { in runOnMachineFunction()
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D | SIInstructions.td | 2184 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1), 2231 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1), 2278 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1), 2301 (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1), 2313 (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1), 2325 (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1), 2337 (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1), 2338 (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1), 2426 (i64 (REG_SEQUENCE SReg_64, 2598 (opcode (REG_SEQUENCE VReg_64, $vsrc, sub0, $vcmp, sub1), [all …]
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D | SIFixSGPRCopies.cpp | 343 case AMDGPU::REG_SEQUENCE: { in runOnMachineFunction()
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D | AMDGPUISelDAGToDAG.cpp | 206 case AMDGPU::REG_SEQUENCE: { in getOperandRegClass() 360 CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(), RegSeqArgs); in Select() 382 ReplaceNode(N, CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, in Select() 413 ReplaceNode(N, CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, in Select() 617 CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, MVT::i64, Args); in SelectADD_SUB_I64()
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D | SIFoldOperands.cpp | 255 if (UseMI->getOpcode() == AMDGPU::REG_SEQUENCE) { in foldOperand()
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/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
D | crash.ll | 31 ; PR10520 - REG_SEQUENCE with implicit-def operands.
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | ResourcePriorityQueue.cpp | 266 case TargetOpcode::REG_SEQUENCE: in isResourceAvailable() 306 case TargetOpcode::REG_SEQUENCE: in reserveResources()
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D | InstrEmitter.cpp | 614 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); in EmitRegSequence() 742 if (Opc == TargetOpcode::REG_SEQUENCE) { in EmitMachineNode()
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonMachineScheduler.cpp | 56 case TargetOpcode::REG_SEQUENCE: in isResourceAvailable() 108 case TargetOpcode::REG_SEQUENCE: in reserveResources()
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D | RDFCopy.cpp | 57 case TargetOpcode::REG_SEQUENCE: { in interpretAsCopy()
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/external/llvm/include/llvm/CodeGen/ |
D | MachineInstr.h | 812 return getOpcode() == TargetOpcode::REG_SEQUENCE; 851 case TargetOpcode::REG_SEQUENCE:
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
D | InstrEmitter.cpp | 569 TII->get(TargetOpcode::REG_SEQUENCE), NewVReg); in EmitRegSequence() 573 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); in EmitRegSequence() 676 if (Opc == TargetOpcode::REG_SEQUENCE) { in EmitMachineNode()
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
D | MachineInstr.h | 282 return getOpcode() == TargetOpcode::REG_SEQUENCE;
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/external/llvm/lib/Target/Sparc/ |
D | SparcISelDAGToDAG.cpp | 269 TargetOpcode::REG_SEQUENCE, dl, MVT::v2i32, in tryInlineAsm()
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