Searched refs:REV64 (Results 1 – 7 of 7) sorted by relevance
| /external/llvm/docs/ |
| D | BigEndianNEON.rst | 194 …REV64 v0.4s, v0.4s // There is no REV128 instruction, so it must be synthesizedcd
195 EXT v0.16b, v0.16b, v0.16b, #8 // with a REV64 then an EXT to swap the two 64-bit elements.
197 REV64 v0.2d, v0.2d
202 …`. For the example above, a ``REV128 4s`` + ``REV128 2d`` is actually a ``REV64 4s``, as shown in …
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 109 REV64, enumerator
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| D | AArch64SchedCyclone.td | 498 // CLS,CLZ,CNT,RBIT,REV16,REV32,REV64,XTN
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| D | AArch64ISelLowering.cpp | 885 case AArch64ISD::REV64: return "AArch64ISD::REV64"; in getTargetNodeName()
5445 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS); in GeneratePerfectShuffle()
5629 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2); in LowerVECTOR_SHUFFLE()
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| D | AArch64InstrInfo.td | 219 def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>;
2880 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>;
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-rev.ll | 221 ; vrev <4 x i16> should use REV32 and not REV64
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 2898 ### REV64 ### subsection
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