| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonIsetDx.td | 17 (outs DoubleRegs:$Rdd),
19 "$Rdd = combine(#1, #$u2)"> {
20 bits<3> Rdd;
26 let Inst{2-0} = Rdd;
65 (outs DoubleRegs:$Rdd),
67 "$Rdd = combine(#3, #$u2)"> {
68 bits<3> Rdd;
74 let Inst{2-0} = Rdd;
196 (outs DoubleRegs:$Rdd),
198 "$Rdd = combine($Rs, #0)"> {
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| D | HexagonInstrAlias.td | 111 def : InstAlias<"$Rdd = memd($Rs)",
112 (L2_loadrd_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>;
117 def : InstAlias<"$Rdd = memubh($Rs)",
118 (L2_loadbzw4_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>;
123 def : InstAlias<"$Rdd = membh($Rs)",
124 (L2_loadbsw4_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>;
126 def : InstAlias<"$Rdd = memb_fifo($Rs)",
127 (L2_loadalignb_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>;
129 def : InstAlias<"$Rdd = memh_fifo($Rs)",
130 (L2_loadalignh_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>;
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| D | HexagonIntrinsicsV4.td | 16 //Rdd=vrmpyweh(Rss,Rtt)[:<<1]
20 //Rdd=vrmpywoh(Rss,Rtt)[:<<1]
24 //Rdd+=vrmpyweh(Rss,Rtt)[:<<1]
28 //Rdd=vrmpywoh(Rss,Rtt)[:<<1]
33 // Rdd=vmpyhsu(Rs,Rt)[:<<1]:sat
42 // Rdd=vpmpyh(Rs,Rt)
48 // Rdd=pmpyw(Rs,Rt)
146 // Rdd=vcnegh(Rss,Rt)
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| D | HexagonInstrInfoV3.td | 200 MInst<(outs DoubleRegs:$Rdd),
202 "$Rdd = vrcmpys($Rss, $Rtt):<<1:sat:raw:"#HiLo, []> {
203 bits<5> Rdd;
214 let Inst{4-0} = Rdd;
223 : MInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
224 "$Rdd=vrcmpys($Rss,$Rt):<<1:sat">;
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| D | HexagonIntrinsicsV5.td | 10 //Rdd[+]=vrmpybsu(Rss,Rtt)
11 //Rdd[+]=vrmpybuu(Rss,Rtt)
24 // Rdd=vmpyb[s]u(Rs,Rt)
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| D | HexagonInstrInfoV5.td | 18 //Rdd[+]=vrmpybsu(Rss,Rtt)
23 //Rdd[+]=vrmpybu(Rss,Rtt)
32 // Rdd=vmpyb[s]u(Rs,Rt)
532 : SInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
533 "$Rdd = "#mnemonic#"($Rss)"#chop,
534 [(set RCOut:$Rdd, (Op RCIn:$Rss))], "",
536 bits<5> Rdd;
544 let Inst{4-0} = Rdd;
551 : SInst <(outs DoubleRegs:$Rdd), (ins IntRegs:$Rs),
552 "$Rdd = "#mnemonic#"($Rs)"#chop,
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| D | HexagonInstrInfo.td | 330 def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8Ext:$s8, s8Imm:$S8),
331 "$Rdd = combine(#$s8, #$S8)",
332 [(set (i64 DoubleRegs:$Rdd),
334 bits<5> Rdd;
343 let Inst{4-0} = Rdd;
856 : ALU64_rr < (outs DoubleRegs:$Rdd),
858 "$Rdd = "#opc#"($Rss, $Rtt)"#!if(isRnd, ":rnd", "")
862 bits<5> Rdd;
873 let Inst{4-0} = Rdd;
877 // Rdd=vadd[u][bhw](Rss,Rtt)
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| D | HexagonSelectCCInfo.td | 96 // selectcc(Rss, Rdd, tval, fval, cond) ->
97 // combine(mux(cmp_cond(Rss, Rdd), tval.hi, fval.hi),
98 // mux(cmp_cond(Rss, Rdd), tval.lo, fval.lo))
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| D | HexagonIntrinsics.td | 412 // Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat
416 // Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat
420 // Vector dual multiply: Rdd=vdmpy(Rss,Rtt)[:<<1]:sat
424 // Vector multiply even halfwords: Rdd=vmpyeh(Rss,Rtt)[:<<1]:sat
428 //Rdd=vmpywoh(Rss,Rtt)[:<<1][:rnd]:sat
434 //Rdd=vmpyweh(Rss,Rtt)[:<<1][:rnd]:sat
440 //Rdd=vmpywouh(Rss,Rtt)[:<<1][:rnd]:sat
446 //Rdd=vmpyweuh(Rss,Rtt)[:<<1][:rnd]:sat
456 // Vector sum of absolute differences unsigned bytes: Rdd=vrsadub(Rss,Rtt)
460 // Vector absolute difference: Rdd=vabsdiffh(Rtt,Rss)
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| D | HexagonInstrInfoV4.td | 296 : ALU32Inst <(outs DoubleRegs:$Rdd), ins, AsmStr> {
297 bits<5> Rdd;
307 let Inst{4-0} = Rdd;
312 "$Rdd = combine($Rs, #$s8)">;
316 "$Rdd = combine(#$s8, $Rs)">;
330 def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8Imm:$s8, u6Ext:$U6),
331 "$Rdd = combine(#$s8, #$U6)"> {
332 bits<5> Rdd;
341 let Inst{4-0} = Rdd;
388 // Map Rdd = anyext(Rs) -> Rdd = combine(#0, Rs).
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| D | HexagonAsmPrinter.cpp | 480 MCOperand &Rdd = MappedInst.getOperand(0); in HexagonProcessInstruction() local
484 TmpInst.addOperand(Rdd); in HexagonProcessInstruction()
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| D | HexagonInstrInfoV60.td | 2180 // defm S2_cabacencbin : _VV <"Rdd=encbin(Rss,$src2,Pu)">, S2_cabacencbin_enc;
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| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1460 MCInst makeCombineInst(int opCode, MCOperand &Rdd, in makeCombineInst() argument
1464 TmpInst.addOperand(Rdd); in makeCombineInst()
1771 MCOperand &Rdd = Inst.getOperand(0); in processInstruction() local
1777 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, imm, MO); in processInstruction()
1783 MCOperand &Rdd = Inst.getOperand(0); in processInstruction() local
1796 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2); in processInstruction()
1800 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, MO); in processInstruction()
1807 MCOperand &Rdd = Inst.getOperand(0); in processInstruction() local
1816 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2); in processInstruction()
1822 MCOperand &Rdd = Inst.getOperand(0); in processInstruction() local
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