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1//==- HexagonInstrAlias.td - Hexagon Instruction Aliases ---*- tablegen -*--==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//                     Hexagon Instruction Mappings
10//===----------------------------------------------------------------------===//
11
12
13def : InstAlias<"memb({GP}+#$addr) = $Nt.new",
14                (S2_storerbnewgp u16_0Imm:$addr, IntRegs:$Nt)>;
15def : InstAlias<"memh({GP}+#$addr) = $Nt.new",
16                (S2_storerhnewgp u16_1Imm:$addr, IntRegs:$Nt)>;
17def : InstAlias<"memw({GP}+#$addr) = $Nt.new",
18                (S2_storerinewgp u16_2Imm:$addr, IntRegs:$Nt)>;
19def : InstAlias<"memb({GP}+#$addr) = $Nt",
20                (S2_storerbgp u16_0Imm:$addr, IntRegs:$Nt)>;
21def : InstAlias<"memh({GP}+#$addr) = $Nt",
22                (S2_storerhgp u16_1Imm:$addr, IntRegs:$Nt)>;
23def : InstAlias<"memh({GP}+#$addr) = $Nt.h",
24                (S2_storerfgp u16_1Imm:$addr, IntRegs:$Nt)>;
25def : InstAlias<"memw({GP}+#$addr) = $Nt",
26                (S2_storerigp u16_2Imm:$addr, IntRegs:$Nt)>;
27def : InstAlias<"memd({GP}+#$addr) = $Nt",
28                (S2_storerdgp u16_3Imm:$addr, DoubleRegs:$Nt)>;
29
30def : InstAlias<"$Nt = memb({GP}+#$addr)",
31                (L2_loadrbgp IntRegs:$Nt, u16_0Imm:$addr)>;
32def : InstAlias<"$Nt = memub({GP}+#$addr)",
33                (L2_loadrubgp IntRegs:$Nt, u16_0Imm:$addr)>;
34def : InstAlias<"$Nt = memh({GP}+#$addr)",
35                (L2_loadrhgp IntRegs:$Nt, u16_1Imm:$addr)>;
36def : InstAlias<"$Nt = memuh({GP}+#$addr)",
37                (L2_loadruhgp IntRegs:$Nt, u16_1Imm:$addr)>;
38def : InstAlias<"$Nt = memw({GP}+#$addr)",
39                (L2_loadrigp IntRegs:$Nt, u16_2Imm:$addr)>;
40def : InstAlias<"$Nt = memd({GP}+#$addr)",
41                (L2_loadrdgp DoubleRegs:$Nt, u16_3Imm:$addr)>;
42
43// Alias of: memXX($Rs+#XX) = $Rt to memXX($Rs) = $Rt
44def : InstAlias<"memb($Rs) = $Rt",
45      (S2_storerb_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
46
47def : InstAlias<"memh($Rs) = $Rt",
48      (S2_storerh_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
49
50def : InstAlias<"memh($Rs) = $Rt.h",
51      (S2_storerf_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
52
53def : InstAlias<"memw($Rs) = $Rt",
54      (S2_storeri_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
55
56def : InstAlias<"memb($Rs) = $Rt.new",
57      (S2_storerbnew_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
58
59def : InstAlias<"memh($Rs) = $Rt.new",
60      (S2_storerhnew_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
61
62def : InstAlias<"memw($Rs) = $Rt.new",
63      (S2_storerinew_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
64
65def : InstAlias<"memb($Rs) = #$S8",
66      (S4_storeirb_io IntRegs:$Rs, 0, s8Ext:$S8), 0>;
67
68def : InstAlias<"memh($Rs) = #$S8",
69      (S4_storeirh_io IntRegs:$Rs, 0, s8Ext:$S8), 0>;
70
71def : InstAlias<"memw($Rs) = #$S8",
72      (S4_storeiri_io IntRegs:$Rs, 0, s8Ext:$S8), 0>;
73
74def : InstAlias<"memd($Rs) = $Rtt",
75      (S2_storerd_io IntRegs:$Rs, 0, DoubleRegs:$Rtt), 0>;
76
77def : InstAlias<"memb($Rs) = setbit(#$U5)",
78      (L4_ior_memopb_io IntRegs:$Rs, 0, u5Imm:$U5), 0>;
79
80def : InstAlias<"memh($Rs) = setbit(#$U5)",
81      (L4_ior_memoph_io IntRegs:$Rs, 0, u5Imm:$U5), 0>;
82
83def : InstAlias<"memw($Rs) = setbit(#$U5)",
84      (L4_ior_memopw_io IntRegs:$Rs, 0, u5Imm:$U5), 0>;
85
86def : InstAlias<"memb($Rs) = clrbit(#$U5)",
87      (L4_iand_memopb_io IntRegs:$Rs, 0, u5Imm:$U5), 0>;
88
89def : InstAlias<"memh($Rs) = clrbit(#$U5)",
90      (L4_iand_memoph_io IntRegs:$Rs, 0, u5Imm:$U5), 0>;
91
92def : InstAlias<"memw($Rs) = clrbit(#$U5)",
93      (L4_iand_memopw_io IntRegs:$Rs, 0, u5Imm:$U5), 0>;
94
95// Alias of: $Rd = memXX($Rs+#XX) to $Rd = memXX($Rs)
96def : InstAlias<"$Rd = memb($Rs)",
97      (L2_loadrb_io IntRegs:$Rd, IntRegs:$Rs, 0), 0>;
98
99def : InstAlias<"$Rd = memub($Rs)",
100      (L2_loadrub_io IntRegs:$Rd, IntRegs:$Rs, 0), 0>;
101
102def : InstAlias<"$Rd = memh($Rs)",
103      (L2_loadrh_io IntRegs:$Rd, IntRegs:$Rs, 0), 0>;
104
105def : InstAlias<"$Rd = memuh($Rs)",
106      (L2_loadruh_io IntRegs:$Rd, IntRegs:$Rs, 0), 0>;
107
108def : InstAlias<"$Rd = memw($Rs)",
109      (L2_loadri_io IntRegs:$Rd, IntRegs:$Rs, 0), 0>;
110
111def : InstAlias<"$Rdd = memd($Rs)",
112      (L2_loadrd_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>;
113
114def : InstAlias<"$Rd = memubh($Rs)",
115      (L2_loadbzw2_io IntRegs:$Rd, IntRegs:$Rs, 0), 0>;
116
117def : InstAlias<"$Rdd = memubh($Rs)",
118      (L2_loadbzw4_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>;
119
120def : InstAlias<"$Rd = membh($Rs)",
121      (L2_loadbsw2_io IntRegs:$Rd, IntRegs:$Rs, 0), 0>;
122
123def : InstAlias<"$Rdd = membh($Rs)",
124      (L2_loadbsw4_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>;
125
126def : InstAlias<"$Rdd = memb_fifo($Rs)",
127      (L2_loadalignb_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>;
128
129def : InstAlias<"$Rdd = memh_fifo($Rs)",
130      (L2_loadalignh_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>;
131
132// Alias of: if ($Pt) $Rd = memXX($Rs + #$u6_X)
133//       to: if ($Pt) $Rd = memXX($Rs)
134def : InstAlias<"if ($Pt) $Rd = memb($Rs)",
135      (L2_ploadrbt_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
136
137def : InstAlias<"if ($Pt) $Rd = memub($Rs)",
138      (L2_ploadrubt_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
139
140def : InstAlias<"if ($Pt) $Rd = memh($Rs)",
141      (L2_ploadrht_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
142
143def : InstAlias<"if ($Pt) $Rd = memuh($Rs)",
144      (L2_ploadruht_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
145
146def : InstAlias<"if ($Pt) $Rd = memw($Rs)",
147      (L2_ploadrit_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
148
149def : InstAlias<"if ($Pt) $Rdd = memd($Rs)",
150      (L2_ploadrdt_io DoubleRegs:$Rdd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
151
152// Alias of: if ($Pt) memXX($Rs + #$u6_X) = $Rt
153//       to: if ($Pt) memXX($Rs) = $Rt
154def : InstAlias<"if ($Pt) memb($Rs) = $Rt",
155      (S2_pstorerbt_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
156
157def : InstAlias<"if ($Pt) memh($Rs) = $Rt",
158      (S2_pstorerht_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
159
160def : InstAlias<"if ($Pt) memh($Rs) = $Rt.h",
161      (S2_pstorerft_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
162
163def : InstAlias<"if ($Pt) memw($Rs) = $Rt",
164      (S2_pstorerit_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
165
166def : InstAlias<"if ($Pt) memd($Rs) = $Rtt",
167      (S2_pstorerdt_io PredRegs:$Pt, IntRegs:$Rs, 0, DoubleRegs:$Rtt), 0>;
168
169def : InstAlias<"if ($Pt) memb($Rs) = $Rt.new",
170      (S2_pstorerbnewt_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
171
172def : InstAlias<"if ($Pt) memh($Rs) = $Rt.new",
173      (S2_pstorerhnewt_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
174
175def : InstAlias<"if ($Pt) memw($Rs) = $Rt.new",
176      (S2_pstorerinewt_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
177
178def : InstAlias<"if ($Pt.new) memb($Rs) = $Rt.new",
179      (S4_pstorerbnewtnew_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
180
181def : InstAlias<"if ($Pt.new) memh($Rs) = $Rt.new",
182      (S4_pstorerhnewtnew_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
183
184def : InstAlias<"if ($Pt.new) memw($Rs) = $Rt.new",
185      (S4_pstorerinewtnew_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
186
187
188// Alias of: if (!$Pt) $Rd = memXX($Rs + #$u6_X)
189//       to: if (!$Pt) $Rd = memXX($Rs)
190def : InstAlias<"if (!$Pt) $Rd = memb($Rs)",
191      (L2_ploadrbf_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
192
193def : InstAlias<"if (!$Pt) $Rd = memub($Rs)",
194      (L2_ploadrubf_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
195
196def : InstAlias<"if (!$Pt) $Rd = memh($Rs)",
197      (L2_ploadrhf_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
198
199def : InstAlias<"if (!$Pt) $Rd = memuh($Rs)",
200      (L2_ploadruhf_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
201
202def : InstAlias<"if (!$Pt) $Rd = memw($Rs)",
203      (L2_ploadrif_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
204
205def : InstAlias<"if (!$Pt) $Rdd = memd($Rs)",
206      (L2_ploadrdf_io DoubleRegs:$Rdd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
207
208// Alias of: if (!$Pt) memXX($Rs + #$u6_X) = $Rt
209//       to: if (!$Pt) memXX($Rs) = $Rt
210def : InstAlias<"if (!$Pt) memb($Rs) = $Rt",
211      (S2_pstorerbf_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
212
213def : InstAlias<"if (!$Pt) memh($Rs) = $Rt",
214      (S2_pstorerhf_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
215
216def : InstAlias<"if (!$Pt) memh($Rs) = $Rt.h",
217      (S2_pstorerff_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
218
219def : InstAlias<"if (!$Pt) memw($Rs) = $Rt",
220      (S2_pstorerif_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
221
222def : InstAlias<"if (!$Pt) memd($Rs) = $Rtt",
223      (S2_pstorerdf_io PredRegs:$Pt, IntRegs:$Rs, 0, DoubleRegs:$Rtt), 0>;
224
225def : InstAlias<"if (!$Pt) memb($Rs) = $Rt.new",
226      (S2_pstorerbnewf_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
227
228def : InstAlias<"if (!$Pt) memh($Rs) = $Rt.new",
229      (S2_pstorerhnewf_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
230
231def : InstAlias<"if (!$Pt) memw($Rs) = $Rt.new",
232      (S2_pstorerinewf_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
233
234def : InstAlias<"if (!$Pt.new) memb($Rs) = $Rt.new",
235      (S4_pstorerbnewfnew_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
236
237def : InstAlias<"if (!$Pt.new) memh($Rs) = $Rt.new",
238      (S4_pstorerhnewfnew_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
239
240def : InstAlias<"if (!$Pt.new) memw($Rs) = $Rt.new",
241      (S4_pstorerinewfnew_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
242
243def : InstAlias<"if ($Pt) memb($Rs) = #$S6",
244      (S4_storeirbt_io PredRegs:$Pt, IntRegs:$Rs, 0, s6Ext:$S6), 0>;
245
246def : InstAlias<"if ($Pt) memh($Rs) = #$S6",
247      (S4_storeirht_io PredRegs:$Pt, IntRegs:$Rs, 0, s6Ext:$S6), 0>;
248
249def : InstAlias<"if ($Pt) memw($Rs) = #$S6",
250      (S4_storeirit_io PredRegs:$Pt, IntRegs:$Rs, 0, s6Ext:$S6), 0>;
251
252def : InstAlias<"if ($Pt.new) memb($Rs) = #$S6",
253      (S4_storeirbtnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6Ext:$S6), 0>;
254
255def : InstAlias<"if ($Pt.new) memh($Rs) = #$S6",
256      (S4_storeirhtnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6Ext:$S6), 0>;
257
258def : InstAlias<"if ($Pt.new) memw($Rs) = #$S6",
259      (S4_storeiritnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6Ext:$S6), 0>;
260
261def : InstAlias<"if (!$Pt) memb($Rs) = #$S6",
262      (S4_storeirbf_io PredRegs:$Pt, IntRegs:$Rs, 0, s6Ext:$S6), 0>;
263
264def : InstAlias<"if (!$Pt) memh($Rs) = #$S6",
265      (S4_storeirhf_io PredRegs:$Pt, IntRegs:$Rs, 0, s6Ext:$S6), 0>;
266
267def : InstAlias<"if (!$Pt) memw($Rs) = #$S6",
268      (S4_storeirif_io PredRegs:$Pt, IntRegs:$Rs, 0, s6Ext:$S6), 0>;
269
270def : InstAlias<"if (!$Pt.new) memb($Rs) = #$S6",
271      (S4_storeirbfnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6Ext:$S6), 0>;
272
273def : InstAlias<"if (!$Pt.new) memh($Rs) = #$S6",
274      (S4_storeirhfnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6Ext:$S6), 0>;
275
276def : InstAlias<"if (!$Pt.new) memw($Rs) = #$S6",
277      (S4_storeirifnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6Ext:$S6), 0>;
278
279// Alias of: memXX($Rs + $u6_X) |= $Rt, also &=, +=, -=
280//       to: memXX($Rs) |= $Rt
281def : InstAlias<"memb($Rs) &= $Rt",
282      (L4_and_memopb_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>,
283      Requires<[UseMEMOP]>;
284
285def : InstAlias<"memb($Rs) |= $Rt",
286      (L4_or_memopb_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>,
287      Requires<[UseMEMOP]>;
288
289def : InstAlias<"memb($Rs) += $Rt",
290      (L4_add_memopb_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>,
291      Requires<[UseMEMOP]>;
292
293def : InstAlias<"memb($Rs) -= $Rt",
294      (L4_sub_memopb_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>,
295      Requires<[UseMEMOP]>;
296
297def : InstAlias<"memb($Rs) += #$U5",
298      (L4_iadd_memopb_io IntRegs:$Rs, 0, u5Imm:$U5), 0>,
299      Requires<[UseMEMOP]>;
300
301def : InstAlias<"memb($Rs) -= #$U5",
302      (L4_isub_memopb_io IntRegs:$Rs, 0, u5Imm:$U5), 0>,
303      Requires<[UseMEMOP]>;
304
305def : InstAlias<"memh($Rs) &= $Rt",
306      (L4_and_memoph_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>,
307      Requires<[UseMEMOP]>;
308
309def : InstAlias<"memh($Rs) |= $Rt",
310      (L4_or_memoph_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>,
311      Requires<[UseMEMOP]>;
312
313def : InstAlias<"memh($Rs) += $Rt",
314      (L4_add_memoph_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>,
315      Requires<[UseMEMOP]>;
316
317def : InstAlias<"memh($Rs) -= $Rt",
318      (L4_sub_memoph_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>,
319      Requires<[UseMEMOP]>;
320
321def : InstAlias<"memh($Rs) += #$U5",
322      (L4_iadd_memoph_io IntRegs:$Rs, 0, u5Imm:$U5), 0>,
323      Requires<[UseMEMOP]>;
324
325def : InstAlias<"memh($Rs) -= #$U5",
326      (L4_isub_memoph_io IntRegs:$Rs, 0, u5Imm:$U5), 0>,
327      Requires<[UseMEMOP]>;
328
329def : InstAlias<"memw($Rs) &= $Rt",
330      (L4_and_memopw_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>,
331      Requires<[UseMEMOP]>;
332
333def : InstAlias<"memw($Rs) |= $Rt",
334      (L4_or_memopw_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>,
335      Requires<[UseMEMOP]>;
336
337def : InstAlias<"memw($Rs) += $Rt",
338      (L4_add_memopw_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>,
339      Requires<[UseMEMOP]>;
340
341def : InstAlias<"memw($Rs) -= $Rt",
342      (L4_sub_memopw_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>,
343      Requires<[UseMEMOP]>;
344
345def : InstAlias<"memw($Rs) += #$U5",
346      (L4_iadd_memopw_io IntRegs:$Rs, 0, u5Imm:$U5), 0>,
347      Requires<[UseMEMOP]>;
348
349def : InstAlias<"memw($Rs) -= #$U5",
350      (L4_isub_memopw_io IntRegs:$Rs, 0, u5Imm:$U5), 0>,
351      Requires<[UseMEMOP]>;
352
353//
354// Alias of: if ($Pv.new) memX($Rs) = $Rt
355//       to: if (p3.new) memX(r17 + #0) = $Rt
356def : InstAlias<"if ($Pv.new) memb($Rs) = $Rt",
357      (S4_pstorerbtnew_io PredRegs:$Pv, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
358
359def : InstAlias<"if ($Pv.new) memh($Rs) = $Rt",
360      (S4_pstorerhtnew_io PredRegs:$Pv, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
361
362def : InstAlias<"if ($Pv.new) memh($Rs) = $Rt.h",
363      (S4_pstorerftnew_io PredRegs:$Pv, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
364
365def : InstAlias<"if ($Pv.new) memw($Rs) = $Rt",
366      (S4_pstoreritnew_io PredRegs:$Pv, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
367
368def : InstAlias<"if ($Pv.new) memd($Rs) = $Rtt",
369      (S4_pstorerdtnew_io
370       PredRegs:$Pv, IntRegs:$Rs, 0, DoubleRegs:$Rtt), 0>;
371
372def : InstAlias<"if (!$Pv.new) memb($Rs) = $Rt",
373      (S4_pstorerbfnew_io PredRegs:$Pv, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
374
375def : InstAlias<"if (!$Pv.new) memh($Rs) = $Rt",
376      (S4_pstorerhfnew_io PredRegs:$Pv, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
377
378def : InstAlias<"if (!$Pv.new) memh($Rs) = $Rt.h",
379      (S4_pstorerffnew_io PredRegs:$Pv, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
380
381def : InstAlias<"if (!$Pv.new) memw($Rs) = $Rt",
382      (S4_pstorerifnew_io PredRegs:$Pv, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
383
384def : InstAlias<"if (!$Pv.new) memd($Rs) = $Rtt",
385      (S4_pstorerdfnew_io
386       PredRegs:$Pv, IntRegs:$Rs, 0, DoubleRegs:$Rtt), 0>;
387
388//
389// Alias of: if ($Pt.new) $Rd = memub($Rs) -- And if (!$Pt.new) ...
390//       to: if ($Pt.new) $Rd = memub($Rs + #$u6_0)
391def : InstAlias<"if ($Pt.new) $Rd = memub($Rs)",
392      (L2_ploadrubtnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
393
394def : InstAlias<"if ($Pt.new) $Rd = memb($Rs)",
395      (L2_ploadrbtnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
396
397def : InstAlias<"if ($Pt.new) $Rd = memh($Rs)",
398      (L2_ploadrhtnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
399
400def : InstAlias<"if ($Pt.new) $Rd = memuh($Rs)",
401      (L2_ploadruhtnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
402
403def : InstAlias<"if ($Pt.new) $Rd = memw($Rs)",
404      (L2_ploadritnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
405
406def : InstAlias<"if ($Pt.new) $Rdd = memd($Rs)",
407      (L2_ploadrdtnew_io DoubleRegs:$Rdd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
408
409def : InstAlias<"if (!$Pt.new) $Rd = memub($Rs)",
410      (L2_ploadrubfnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
411
412def : InstAlias<"if (!$Pt.new) $Rd = memb($Rs)",
413      (L2_ploadrbfnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
414
415def : InstAlias<"if (!$Pt.new) $Rd = memh($Rs)",
416      (L2_ploadrhfnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
417
418def : InstAlias<"if (!$Pt.new) $Rd = memuh($Rs)",
419      (L2_ploadruhfnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
420
421def : InstAlias<"if (!$Pt.new) $Rd = memw($Rs)",
422      (L2_ploadrifnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
423
424def : InstAlias<"if (!$Pt.new) $Rdd = memd($Rs)",
425      (L2_ploadrdfnew_io DoubleRegs:$Rdd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>;
426
427def : InstAlias<"dcfetch($Rs)",
428      (Y2_dcfetchbo IntRegs:$Rs, 0), 0>;
429
430// Alias of some insn mappings, others must be handled by the parser
431def : InstAlias<"$Pd=cmp.lt($Rs, $Rt)",
432      (C2_cmpgt PredRegs:$Pd, IntRegs:$Rt, IntRegs:$Rs), 0>;
433def : InstAlias<"$Pd=cmp.ltu($Rs, $Rt)",
434      (C2_cmpgtu PredRegs:$Pd, IntRegs:$Rt, IntRegs:$Rs), 0>;
435
436// Rd=neg(Rs) is aliased to Rd=sub(#0,Rs)
437def : InstAlias<"$Rd = neg($Rs)",
438      (A2_subri IntRegs:$Rd, 0, IntRegs:$Rs), 0>;
439
440def : InstAlias<"m0 = $Rs", (A2_tfrrcr C6, IntRegs:$Rs)>;
441def : InstAlias<"$Rd = m0", (A2_tfrcrr IntRegs:$Rd, C6)>;
442def : InstAlias<"m1 = $Rs", (A2_tfrrcr C7, IntRegs:$Rs)>;
443def : InstAlias<"$Rd = m1", (A2_tfrcrr IntRegs:$Rd, C7)>;
444
445def : InstAlias<"$Pd = $Ps",
446      (C2_or PredRegs:$Pd, PredRegs:$Ps, PredRegs:$Ps), 0>;
447
448def : InstAlias<"$Rdd = vaddb($Rss, $Rtt)",
449      (A2_vaddub DoubleRegs:$Rdd, DoubleRegs:$Rss, DoubleRegs:$Rtt), 1>;
450
451def : InstAlias<"$Rdd = vsubb($Rss,$Rtt)",
452      (A2_vsubub DoubleRegs:$Rdd, DoubleRegs:$Rss, DoubleRegs:$Rtt), 0>;
453
454def : InstAlias<"$Rd = mpyui($Rs,$Rt)",
455      (M2_mpyi IntRegs:$Rd, IntRegs:$Rs, IntRegs:$Rt), 0>;
456
457// Assembler mapped insns: cmp.lt(a,b) -> cmp.gt(b,a)
458def : InstAlias<"$Pd=cmp.lt($Rs, $Rt)",
459      (C2_cmpgt PredRegs:$Pd, IntRegs:$Rt, IntRegs:$Rs), 0>;
460def : InstAlias<"$Pd=cmp.ltu($Rs, $Rt)",
461      (C2_cmpgtu PredRegs:$Pd, IntRegs:$Rt, IntRegs:$Rs), 0>;
462
463// maps if (!Pu) jumpr Rs -> if (!Pu) jumpr:nt Rs
464def : InstAlias<"if (!$Pu) jumpr $Rs",
465      (J2_jumprf PredRegs:$Pu, IntRegs:$Rs)>,
466      Requires<[HasV60T]>;
467
468// maps if (Pu) jumpr Rs -> if (Pu) jumpr:nt Rs
469def : InstAlias<"if ($Pu) jumpr $Rs",
470      (J2_jumprt PredRegs:$Pu, IntRegs:$Rs)>,
471      Requires<[HasV60T]>;
472
473// maps if (!Pu) jump $r15_2 -> if (!Pu) jump:nt $r15_2
474def : InstAlias<"if (!$Pu) jump $r15_2",
475      (J2_jumpf PredRegs:$Pu, brtarget:$r15_2)>,
476      Requires<[HasV60T]>;
477
478// maps if (Pu) jump $r15_2 -> if (Pu) jump:nt $r15_2
479def : InstAlias<"if ($Pu) jump $r15_2",
480     (J2_jumpt PredRegs:$Pu, brtarget:$r15_2)>,
481     Requires<[HasV60T]>;
482
483def : InstAlias<"if ($src) jump $r15_2",
484      (J2_jumpt PredRegs:$src, brtarget:$r15_2), 0>;
485
486def : InstAlias<"if (!$src) jump $r15_2",
487      (J2_jumpf PredRegs:$src, brtarget:$r15_2), 0>;
488
489def : InstAlias<"if ($src1) jumpr $src2",
490      (J2_jumprt PredRegs:$src1, IntRegs:$src2), 0>;
491
492def : InstAlias<"if (!$src1) jumpr $src2",
493      (J2_jumprf PredRegs:$src1, IntRegs:$src2), 0>;
494
495// V6_vassignp: Vector assign mapping.
496let hasNewValue = 1, opNewValue = 0, isAsmParserOnly = 1 in
497def HEXAGON_V6_vassignpair: CVI_VA_DV_Resource <
498  (outs VecDblRegs:$Vdd),
499  (ins VecDblRegs:$Vss),
500  "$Vdd = $Vss">;
501
502// maps Vd = #0 to Vd = vxor(Vd, Vd)
503def : InstAlias<"$Vd = #0",
504      (V6_vxor VectorRegs:$Vd, VectorRegs:$Vd, VectorRegs:$Vd)>,
505      Requires<[HasV60T]>;
506
507// maps Vdd  = #0 to Vdd = vsub(Vdd, Vdd)
508def : InstAlias<"$Vdd = #0",
509      (V6_vsubw_dv VecDblRegs:$Vdd, VecDblRegs:$Vdd, VecDblRegs:$Vdd)>,
510      Requires<[HasV60T]>;
511
512// maps   "$Qd = vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd = vcmp.eq($Vu.h, $Vv.h)"
513def : InstAlias<"$Qd = vcmp.eq($Vu.uh, $Vv.uh)",
514      (V6_veqh VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
515      Requires<[HasV60T]>;
516
517// maps   "$Qd &= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd &= vcmp.eq($Vu.h, $Vv.h)"
518def : InstAlias<"$Qd &= vcmp.eq($Vu.uh, $Vv.uh)",
519      (V6_veqh_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
520      Requires<[HasV60T]>;
521
522// maps   "$Qd |= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd |= vcmp.eq($Vu.h, $Vv.h)"
523def : InstAlias<"$Qd |= vcmp.eq($Vu.uh, $Vv.uh)",
524      (V6_veqh_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
525      Requires<[HasV60T]>;
526
527// maps   "$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd ^= vcmp.eq($Vu.h, $Vv.h)"
528def : InstAlias<"$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)",
529      (V6_veqh_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
530      Requires<[HasV60T]>;
531
532// maps   "$Qd = vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd = vcmp.eq($Vu.w, $Vv.w)"
533def : InstAlias<"$Qd = vcmp.eq($Vu.uw, $Vv.uw)",
534      (V6_veqw VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
535      Requires<[HasV60T]>;
536
537// maps   "$Qd &= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd &= vcmp.eq($Vu.w, $Vv.w)"
538def : InstAlias<"$Qd &= vcmp.eq($Vu.uw, $Vv.uw)",
539      (V6_veqw_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
540      Requires<[HasV60T]>;
541
542// maps   "$Qd |= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd |= vcmp.eq($Vu.w, $Vv.w)"
543def : InstAlias<"$Qd |= vcmp.eq($Vu.uw, $Vv.uw)",
544      (V6_veqh_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
545      Requires<[HasV60T]>;
546
547// maps   "$Qd ^= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd ^= vcmp.eq($Vu.w, $Vv.w)"
548def : InstAlias<"$Qd ^= vcmp.eq($Vu.uw, $Vv.uw)",
549      (V6_veqw_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
550      Requires<[HasV60T]>;
551
552// maps   "$Qd = vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd = vcmp.eq($Vu.b, $Vv.b)"
553def : InstAlias<"$Qd = vcmp.eq($Vu.ub, $Vv.ub)",
554      (V6_veqb VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
555      Requires<[HasV60T]>;
556
557// maps   "$Qd &= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd &= vcmp.eq($Vu.b, $Vv.b)"
558def : InstAlias<"$Qd &= vcmp.eq($Vu.ub, $Vv.ub)",
559      (V6_veqb_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
560      Requires<[HasV60T]>;
561
562// maps   "$Qd |= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd |= vcmp.eq($Vu.b, $Vv.b)"
563def : InstAlias<"$Qd |= vcmp.eq($Vu.ub, $Vv.ub)",
564      (V6_veqb_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
565      Requires<[HasV60T]>;
566
567// maps   "$Qd ^= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd ^= vcmp.eq($Vu.b, $Vv.b)"
568def : InstAlias<"$Qd ^= vcmp.eq($Vu.ub, $Vv.ub)",
569      (V6_veqb_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
570      Requires<[HasV60T]>;
571
572// maps   "$Rd.w = vextract($Vu, $Rs)" -> "$Rd = vextract($Vu, $Rs)"
573def : InstAlias<"$Rd.w = vextract($Vu, $Rs)",
574      (V6_extractw IntRegs:$Rd, VectorRegs:$Vu, IntRegs:$Rs)>,
575      Requires<[HasV60T]>;
576
577// Mapping from vtrans2x2(Vy32,Vx32,Rt32) to vshuff(Vy32,Vx32,Rt32)
578def : InstAlias<"vtrans2x2($Vy, $Vx, $Rt)",
579      (V6_vshuff VectorRegs:$Vy, VectorRegs:$Vx, IntRegs:$Rt)>,
580      Requires<[HasV60T]>;
581
582def : InstAlias<"$Vt=vmem($Rs)",
583      (V6_vL32b_ai VectorRegs:$Vt, IntRegs:$Rs, 0)>,
584      Requires<[HasV60T]>;
585
586def : InstAlias<"$Vt=vmem($Rs):nt",
587      (V6_vL32b_nt_ai VectorRegs:$Vt, IntRegs:$Rs, 0)>,
588      Requires<[HasV60T]>;
589
590def : InstAlias<"vmem($Rs)=$Vt",
591      (V6_vS32b_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>,
592      Requires<[HasV60T]>;
593
594def : InstAlias<"vmem($Rs):nt=$Vt",
595      (V6_vS32b_nt_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>,
596      Requires<[HasV60T]>;
597
598def : InstAlias<"vmem($Rs)=$Vt.new",
599      (V6_vS32b_new_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>,
600      Requires<[HasV60T]>;
601
602def : InstAlias<"vmem($Rs):nt=$Vt.new",
603      (V6_vS32b_nt_new_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>,
604      Requires<[HasV60T]>;
605
606def : InstAlias<"if ($Qv) vmem($Rs)=$Vt",
607      (V6_vS32b_qpred_ai VecPredRegs:$Qv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
608      Requires<[HasV60T]>;
609
610def : InstAlias<"if (!$Qv) vmem($Rs)=$Vt",
611      (V6_vS32b_nqpred_ai VecPredRegs:$Qv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
612      Requires<[HasV60T]>;
613
614def : InstAlias<"if ($Qv) vmem($Rs):nt=$Vt",
615      (V6_vS32b_nt_qpred_ai VecPredRegs:$Qv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
616      Requires<[HasV60T]>;
617
618def : InstAlias<"if (!$Qv) vmem($Rs):nt=$Vt",
619      (V6_vS32b_nt_nqpred_ai VecPredRegs:$Qv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
620      Requires<[HasV60T]>;
621
622def : InstAlias<"if ($Pv) vmem($Rs)=$Vt",
623      (V6_vS32b_pred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
624      Requires<[HasV60T]>;
625
626def : InstAlias<"if (!$Pv) vmem($Rs)=$Vt",
627      (V6_vS32b_npred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
628      Requires<[HasV60T]>;
629
630def : InstAlias<"if ($Pv) vmem($Rs):nt=$Vt",
631      (V6_vS32b_nt_pred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
632      Requires<[HasV60T]>;
633
634def : InstAlias<"if (!$Pv) vmem($Rs):nt=$Vt",
635      (V6_vS32b_nt_npred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
636      Requires<[HasV60T]>;
637
638def : InstAlias<"$Vt=vmemu($Rs)",
639      (V6_vL32Ub_ai VectorRegs:$Vt, IntRegs:$Rs, 0)>,
640      Requires<[HasV60T]>;
641
642def : InstAlias<"vmemu($Rs)=$Vt",
643      (V6_vS32Ub_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>,
644      Requires<[HasV60T]>;
645
646def : InstAlias<"if ($Pv) vmemu($Rs)=$Vt",
647      (V6_vS32Ub_pred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
648      Requires<[HasV60T]>;
649
650def : InstAlias<"if (!$Pv) vmemu($Rs)=$Vt",
651      (V6_vS32Ub_npred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>,
652      Requires<[HasV60T]>;
653
654
655