Searched refs:RecVec (Results 1 – 10 of 10) sorted by relevance
| /external/llvm/utils/TableGen/ |
| D | CodeGenSchedule.h | 30 typedef std::vector<Record*> RecVec; typedef
36 void splitSchedReadWrites(const RecVec &RWDefs,
37 RecVec &WriteDefs, RecVec &ReadDefs);
56 RecVec Aliases;
100 RecVec PredTerm;
143 RecVec InstRWs;
186 RecVec ItinDefList;
190 RecVec ItinRWDefs;
194 RecVec UnsupportedFeaturesDefs;
197 RecVec WriteResDefs;
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| D | CodeGenSchedule.cpp | 139 RecVec ProcRecords = Records.getAllDerivedDefinitions("Processor"); in collectProcModels()
179 static void scanSchedRW(Record *RWDef, RecVec &RWDefs, in scanSchedRW()
186 RecVec Seq = RWDef->getValueAsListOfDefs("Writes"); in scanSchedRW()
192 RecVec Vars = RWDef->getValueAsListOfDefs("Variants"); in scanSchedRW()
195 RecVec Selected = (*VI)->getValueAsListOfDefs("Selected"); in scanSchedRW()
212 RecVec SWDefs, SRDefs; in collectSchedRW()
217 RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW"); in collectSchedRW()
228 RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW"); in collectSchedRW()
231 RecVec RWDefs = (*OI)->getValueAsListOfDefs("OperandReadWrites"); in collectSchedRW()
243 RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW"); in collectSchedRW()
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| D | SubtargetEmitter.cpp | 97 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
617 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources"); in EmitProcessorResources()
753 void SubtargetEmitter::ExpandProcResources(RecVec &PRVec, in ExpandProcResources()
760 RecVec SubResources; in ExpandProcResources()
783 RecVec SuperResources = PR->getValueAsListOfDefs("Resources"); in ExpandProcResources()
875 RecVec Matched = I->getValueAsListOfDefs("MatchedItinClasses"); in GenSchedClassTables()
927 RecVec PRVec = WriteRes->getValueAsListOfDefs("ProcResources"); in GenSchedClassTables()
971 RecVec ValidWrites = ReadAdvance->getValueAsListOfDefs("ValidWrites"); in GenSchedClassTables()
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| D | RegisterInfoEmitter.cpp | 1459 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); in runTargetDesc()
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| D | CodeGenRegisters.cpp | 676 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R); in CodeGenRegisterClass()
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| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | SetTheory.h | 64 typedef std::vector<Record*> RecVec; typedef
88 typedef std::map<Record*, RecVec> ExpandMap;
130 const RecVec *expand(Record *Set);
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| D | SetTheory.cpp | 26 typedef SetTheory::RecVec RecVec; typedef
181 if (const RecVec *Result = ST.expand(Rec)) in apply()
228 if (const RecVec *Result = expand(Def->getDef())) in evaluate()
251 const RecVec *SetTheory::expand(Record *Set) { in expand()
263 RecVec &EltVec = Expansions[Set]; in expand()
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| D | CodeGenRegisters.cpp | 277 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R); in CodeGenRegisterClass()
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| /external/llvm/include/llvm/TableGen/ |
| D | SetTheory.h | 65 typedef std::vector<Record*> RecVec; typedef
94 typedef std::map<Record*, RecVec> ExpandMap;
136 const RecVec *expand(Record *Set);
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| /external/llvm/lib/TableGen/ |
| D | SetTheory.cpp | 26 typedef SetTheory::RecVec RecVec; typedef
220 if (const RecVec *Result = ST.expand(Rec)) in apply()
275 if (const RecVec *Result = expand(Def->getDef())) in evaluate()
298 const RecVec *SetTheory::expand(Record *Set) { in expand()
313 RecVec &EltVec = Expansions[Set]; in expand()
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