Searched refs:RegSeq (Results 1 – 4 of 4) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1030 SDValue RegSeq = createQTuple(Regs); in SelectTable() local
1035 Ops.push_back(RegSeq); in SelectTable()
1195 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectStore() local
1197 SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), N->getOperand(0)}; in SelectStore()
1213 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectPostStore() local
1215 SDValue Ops[] = {RegSeq, in SelectPostStore()
1272 SDValue RegSeq = createQTuple(Regs); in SelectLoadLane() local
1279 SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64), in SelectLoadLane()
1284 EVT WideVT = RegSeq.getOperand(1)->getValueType(0); in SelectLoadLane()
1311 SDValue RegSeq = createQTuple(Regs); in SelectPostLoadLane() local
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1782 SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVST() local
1786 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain }; in SelectVST()
1803 Ops.push_back(RegSeq); in SelectVST()
2018 SDValue RegSeq; in SelectVTBL() local
2022 RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0); in SelectVTBL()
2030 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); in SelectVTBL()
2036 Ops.push_back(RegSeq); in SelectVTBL()
3159 SDValue RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0); in Select() local
3162 Ops.push_back(RegSeq); in Select()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 2061 SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVST() local
2065 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain }; in SelectVST()
2082 Ops.push_back(RegSeq); in SelectVST()
2304 SDValue RegSeq; in SelectVTBL() local
2308 RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0); in SelectVTBL()
2316 RegSeq = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0); in SelectVTBL()
2322 Ops.push_back(RegSeq); in SelectVTBL()
3709 SDValue RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0); in Select() local
3711 SDValue Ops[] = {RegSeq, N->getOperand(2), getAL(CurDAG, dl), // Predicate in Select()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | TwoAddressInstructionPass.cpp | 1417 static bool HasOtherRegSequenceUses(unsigned Reg, MachineInstr *RegSeq, in HasOtherRegSequenceUses() argument
1422 if (UseMI != RegSeq && UseMI->isRegSequence()) in HasOtherRegSequenceUses()
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