| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 725 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal enumerator
752 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 863 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal enumerator
890 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | Analysis.cpp | 165 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; in getFCmpCondCode()
191 case ICmpInst::ICMP_UGE: return ISD::SETUGE; in getICmpCondCode()
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| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 175 case FCmpInst::FCMP_UGE: return ISD::SETUGE; in getFCmpCondCode()
191 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE; in getFCmpCodeWithoutNaN()
206 case ICmpInst::ICMP_UGE: return ISD::SETUGE; in getICmpCondCode()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaISelDAGToDAG.cpp | 319 case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE: in Select()
337 case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE: in Select()
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | README.txt | 77 SETUGE unimplemented
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSelectCCInfo.td | 68 IntRegs:$fval, SETUGE)),
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrInteger.td | 53 defm GE_U : ComparisonInt<SETUGE, "ge_u">;
|
| D | WebAssemblyISelLowering.cpp | 78 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE}) in WebAssemblyTargetLowering()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 243 case ISD::SETUGE: in softenSetCCOperands()
1578 case ISD::SETUGE: in SimplifySetCC()
1601 case ISD::SETUGE: in SimplifySetCC()
1748 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { in SimplifySetCC()
1780 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) in SimplifySetCC()
1876 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || in SimplifySetCC()
1889 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in SimplifySetCC()
1963 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); in SimplifySetCC()
2163 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X in SimplifySetCC()
|
| D | SelectionDAGDumper.cpp | 342 case ISD::SETUGE: return "setuge"; in getOperationName()
|
| D | LegalizeIntegerTypes.cpp | 970 case ISD::SETUGE: in PromoteSetCCOperands()
2840 case ISD::SETUGE: LowCC = ISD::SETUGE; break; in IntegerExpandSetCCOperands()
2873 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || in IntegerExpandSetCCOperands()
2905 case ISD::SETULE: CCCode = ISD::SETUGE; FlipOperands = true; break; in IntegerExpandSetCCOperands()
|
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| D | PTXInstrInfo.td | 552 defm SETPGEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETUGE, "ge">;
565 defm SETPGEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETUGE, "ge">;
578 defm SETPGEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETUGE, "ge">;
591 defm SETPGEf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETUGE, SETOGE, "ge">;
600 defm SETPGEf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETUGE, SETOGE, "ge">;
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrQPX.td | 1010 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETUGE),
1057 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETUGE),
1129 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETUGE)),
1150 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETUGE)),
1171 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETUGE)),
|
| D | PPCInstrInfo.td | 2990 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
3181 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
3209 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
3249 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
3277 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
3304 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
3335 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
3376 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)),
3402 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)),
3423 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)),
[all …]
|
| D | PPCISelDAGToDAG.cpp | 2107 case ISD::SETUGE: in getPredicateForSetCC()
2131 case ISD::SETUGE: in getCRIdxForSetCC()
2164 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
2208 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 2083 case ISD::SETUGE: in SimplifySetCC()
2106 case ISD::SETUGE: in SimplifySetCC()
2239 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { in SimplifySetCC()
2257 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) in SimplifySetCC()
2382 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); in SimplifySetCC()
2567 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X in SimplifySetCC()
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeInstrInfo.td | 778 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETUGE),
815 (i32 GPR:$T), (i32 GPR:$F), SETUGE),
846 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETUGE), bb:$T),
|
| D | MBlazeInstrFPU.td | 196 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUGE),
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 562 case ISD::SETUGE: in getPredicateForSetCC()
590 case ISD::SETUGE: in getCRIdxForSetCC()
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 554 case ISD::SETUGE: in EmitInstrWithCustomInserter()
|
| D | BPFInstrInfo.td | 79 [{return (N->getZExtValue() == ISD::SETUGE);}]>;
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 193 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand); in MipsSETargetLowering()
198 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand); in MipsSETargetLowering()
289 setCondCodeAction(ISD::SETUGE, Ty, Expand); in addMSAIntType()
325 setCondCodeAction(ISD::SETUGE, Ty, Expand); in addMSAFloatType()
966 case ISD::SETUGE: return !IsV216; in isLegalDSPCondCode()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 1003 case ISD::SETUGE: in CombineFMinMaxLegacy()
1397 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE); in LowerUDIVREM64()
1403 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE); in LowerUDIVREM64()
1476 ISD::SETUGE); in LowerUDIVREM()
1482 ISD::SETUGE); in LowerUDIVREM()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 657 case ISD::SETUGE: return SPCC::ICC_CC; in IntCondCCodeToICC()
681 case ISD::SETUGE: return SPCC::FCC_UGE; in FPCondCCodeToFCC()
|