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1//===-- BPFInstrInfo.td - Target Description for BPF Target ---------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the BPF instructions in TableGen format.
11//
12//===----------------------------------------------------------------------===//
13
14include "BPFInstrFormats.td"
15
16// Instruction Operands and Patterns
17
18// These are target-independent nodes, but have target-specific formats.
19def SDT_BPFCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>]>;
20def SDT_BPFCallSeqEnd   : SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
21def SDT_BPFCall         : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
22def SDT_BPFSetFlag      : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
23def SDT_BPFSelectCC     : SDTypeProfile<1, 5, [SDTCisSameAs<1, 2>,
24                                               SDTCisSameAs<0, 4>,
25                                               SDTCisSameAs<4, 5>]>;
26def SDT_BPFBrCC         : SDTypeProfile<0, 4, [SDTCisSameAs<0, 1>,
27                                               SDTCisVT<3, OtherVT>]>;
28def SDT_BPFWrapper      : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
29                                               SDTCisPtrTy<0>]>;
30
31def BPFcall         : SDNode<"BPFISD::CALL", SDT_BPFCall,
32                             [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
33                              SDNPVariadic]>;
34def BPFretflag      : SDNode<"BPFISD::RET_FLAG", SDTNone,
35                             [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
36def BPFcallseq_start: SDNode<"ISD::CALLSEQ_START", SDT_BPFCallSeqStart,
37                             [SDNPHasChain, SDNPOutGlue]>;
38def BPFcallseq_end  : SDNode<"ISD::CALLSEQ_END",   SDT_BPFCallSeqEnd,
39                             [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
40def BPFbrcc         : SDNode<"BPFISD::BR_CC", SDT_BPFBrCC,
41                             [SDNPHasChain, SDNPOutGlue, SDNPInGlue]>;
42
43def BPFselectcc     : SDNode<"BPFISD::SELECT_CC", SDT_BPFSelectCC, [SDNPInGlue]>;
44def BPFWrapper      : SDNode<"BPFISD::Wrapper", SDT_BPFWrapper>;
45
46def brtarget : Operand<OtherVT>;
47def calltarget : Operand<i64>;
48
49def u64imm   : Operand<i64> {
50  let PrintMethod = "printImm64Operand";
51}
52
53def i64immSExt32 : PatLeaf<(imm),
54                [{return isInt<32>(N->getSExtValue()); }]>;
55
56// Addressing modes.
57def ADDRri : ComplexPattern<i64, 2, "SelectAddr", [], []>;
58def FIri : ComplexPattern<i64, 2, "SelectFIAddr", [add, or], []>;
59
60// Address operands
61def MEMri : Operand<i64> {
62  let PrintMethod = "printMemOperand";
63  let EncoderMethod = "getMemoryOpValue";
64  let MIOperandInfo = (ops GPR, i16imm);
65}
66
67// Conditional code predicates - used for pattern matching for jump instructions
68def BPF_CC_EQ  : PatLeaf<(imm),
69                         [{return (N->getZExtValue() == ISD::SETEQ);}]>;
70def BPF_CC_NE  : PatLeaf<(imm),
71                         [{return (N->getZExtValue() == ISD::SETNE);}]>;
72def BPF_CC_GE  : PatLeaf<(imm),
73                         [{return (N->getZExtValue() == ISD::SETGE);}]>;
74def BPF_CC_GT  : PatLeaf<(imm),
75                         [{return (N->getZExtValue() == ISD::SETGT);}]>;
76def BPF_CC_GTU : PatLeaf<(imm),
77                         [{return (N->getZExtValue() == ISD::SETUGT);}]>;
78def BPF_CC_GEU : PatLeaf<(imm),
79                         [{return (N->getZExtValue() == ISD::SETUGE);}]>;
80
81// jump instructions
82class JMP_RR<bits<4> Opc, string OpcodeStr, PatLeaf Cond>
83    : InstBPF<(outs), (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
84              !strconcat(OpcodeStr, "\t$dst, $src goto $BrDst"),
85              [(BPFbrcc i64:$dst, i64:$src, Cond, bb:$BrDst)]> {
86  bits<4> op;
87  bits<1> BPFSrc;
88  bits<4> dst;
89  bits<4> src;
90  bits<16> BrDst;
91
92  let Inst{63-60} = op;
93  let Inst{59} = BPFSrc;
94  let Inst{55-52} = src;
95  let Inst{51-48} = dst;
96  let Inst{47-32} = BrDst;
97
98  let op = Opc;
99  let BPFSrc = 1;
100  let BPFClass = 5; // BPF_JMP
101}
102
103class JMP_RI<bits<4> Opc, string OpcodeStr, PatLeaf Cond>
104    : InstBPF<(outs), (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
105              !strconcat(OpcodeStr, "i\t$dst, $imm goto $BrDst"),
106              [(BPFbrcc i64:$dst, i64immSExt32:$imm, Cond, bb:$BrDst)]> {
107  bits<4> op;
108  bits<1> BPFSrc;
109  bits<4> dst;
110  bits<16> BrDst;
111  bits<32> imm;
112
113  let Inst{63-60} = op;
114  let Inst{59} = BPFSrc;
115  let Inst{51-48} = dst;
116  let Inst{47-32} = BrDst;
117  let Inst{31-0} = imm;
118
119  let op = Opc;
120  let BPFSrc = 0;
121  let BPFClass = 5; // BPF_JMP
122}
123
124multiclass J<bits<4> Opc, string OpcodeStr, PatLeaf Cond> {
125  def _rr : JMP_RR<Opc, OpcodeStr, Cond>;
126  def _ri : JMP_RI<Opc, OpcodeStr, Cond>;
127}
128
129let isBranch = 1, isTerminator = 1, hasDelaySlot=0 in {
130// cmp+goto instructions
131defm JEQ  : J<0x1, "jeq",  BPF_CC_EQ>;
132defm JUGT : J<0x2, "jgt", BPF_CC_GTU>;
133defm JUGE : J<0x3, "jge", BPF_CC_GEU>;
134defm JNE  : J<0x5, "jne",  BPF_CC_NE>;
135defm JSGT : J<0x6, "jsgt", BPF_CC_GT>;
136defm JSGE : J<0x7, "jsge", BPF_CC_GE>;
137}
138
139// ALU instructions
140class ALU_RI<bits<4> Opc, string OpcodeStr, SDNode OpNode>
141    : InstBPF<(outs GPR:$dst), (ins GPR:$src2, i64imm:$imm),
142              !strconcat(OpcodeStr, "i\t$dst, $imm"),
143              [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]> {
144  bits<4> op;
145  bits<1> BPFSrc;
146  bits<4> dst;
147  bits<32> imm;
148
149  let Inst{63-60} = op;
150  let Inst{59} = BPFSrc;
151  let Inst{51-48} = dst;
152  let Inst{31-0} = imm;
153
154  let op = Opc;
155  let BPFSrc = 0;
156  let BPFClass = 7; // BPF_ALU64
157}
158
159class ALU_RR<bits<4> Opc, string OpcodeStr, SDNode OpNode>
160    : InstBPF<(outs GPR:$dst), (ins GPR:$src2, GPR:$src),
161              !strconcat(OpcodeStr, "\t$dst, $src"),
162              [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]> {
163  bits<4> op;
164  bits<1> BPFSrc;
165  bits<4> dst;
166  bits<4> src;
167
168  let Inst{63-60} = op;
169  let Inst{59} = BPFSrc;
170  let Inst{55-52} = src;
171  let Inst{51-48} = dst;
172
173  let op = Opc;
174  let BPFSrc = 1;
175  let BPFClass = 7; // BPF_ALU64
176}
177
178multiclass ALU<bits<4> Opc, string OpcodeStr, SDNode OpNode> {
179  def _rr : ALU_RR<Opc, OpcodeStr, OpNode>;
180  def _ri : ALU_RI<Opc, OpcodeStr, OpNode>;
181}
182
183let Constraints = "$dst = $src2" in {
184let isAsCheapAsAMove = 1 in {
185  defm ADD : ALU<0x0, "add", add>;
186  defm SUB : ALU<0x1, "sub", sub>;
187  defm OR  : ALU<0x4, "or", or>;
188  defm AND : ALU<0x5, "and", and>;
189  defm SLL : ALU<0x6, "sll", shl>;
190  defm SRL : ALU<0x7, "srl", srl>;
191  defm XOR : ALU<0xa, "xor", xor>;
192  defm SRA : ALU<0xc, "sra", sra>;
193}
194  defm MUL : ALU<0x2, "mul", mul>;
195  defm DIV : ALU<0x3, "div", udiv>;
196}
197
198class MOV_RR<string OpcodeStr>
199    : InstBPF<(outs GPR:$dst), (ins GPR:$src),
200              !strconcat(OpcodeStr, "\t$dst, $src"),
201              []> {
202  bits<4> op;
203  bits<1> BPFSrc;
204  bits<4> dst;
205  bits<4> src;
206
207  let Inst{63-60} = op;
208  let Inst{59} = BPFSrc;
209  let Inst{55-52} = src;
210  let Inst{51-48} = dst;
211
212  let op = 0xb;     // BPF_MOV
213  let BPFSrc = 1;   // BPF_X
214  let BPFClass = 7; // BPF_ALU64
215}
216
217class MOV_RI<string OpcodeStr>
218    : InstBPF<(outs GPR:$dst), (ins i64imm:$imm),
219              !strconcat(OpcodeStr, "\t$dst, $imm"),
220              [(set GPR:$dst, (i64 i64immSExt32:$imm))]> {
221  bits<4> op;
222  bits<1> BPFSrc;
223  bits<4> dst;
224  bits<32> imm;
225
226  let Inst{63-60} = op;
227  let Inst{59} = BPFSrc;
228  let Inst{51-48} = dst;
229  let Inst{31-0} = imm;
230
231  let op = 0xb;     // BPF_MOV
232  let BPFSrc = 0;   // BPF_K
233  let BPFClass = 7; // BPF_ALU64
234}
235
236class LD_IMM64<bits<4> Pseudo, string OpcodeStr>
237    : InstBPF<(outs GPR:$dst), (ins u64imm:$imm),
238              !strconcat(OpcodeStr, "\t$dst, $imm"),
239              [(set GPR:$dst, (i64 imm:$imm))]> {
240
241  bits<3> mode;
242  bits<2> size;
243  bits<4> dst;
244  bits<64> imm;
245
246  let Inst{63-61} = mode;
247  let Inst{60-59} = size;
248  let Inst{51-48} = dst;
249  let Inst{55-52} = Pseudo;
250  let Inst{47-32} = 0;
251  let Inst{31-0} = imm{31-0};
252
253  let mode = 0;     // BPF_IMM
254  let size = 3;     // BPF_DW
255  let BPFClass = 0; // BPF_LD
256}
257
258let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
259def LD_imm64 : LD_IMM64<0, "ld_64">;
260def MOV_rr : MOV_RR<"mov">;
261def MOV_ri : MOV_RI<"mov">;
262}
263
264def FI_ri
265    : InstBPF<(outs GPR:$dst), (ins MEMri:$addr),
266               "lea\t$dst, $addr",
267               [(set i64:$dst, FIri:$addr)]> {
268  // This is a tentative instruction, and will be replaced
269  // with MOV_rr and ADD_ri in PEI phase
270}
271
272
273def LD_pseudo
274    : InstBPF<(outs GPR:$dst), (ins i64imm:$pseudo, u64imm:$imm),
275              "ld_pseudo\t$dst, $pseudo, $imm",
276              [(set GPR:$dst, (int_bpf_pseudo imm:$pseudo, imm:$imm))]> {
277
278  bits<3> mode;
279  bits<2> size;
280  bits<4> dst;
281  bits<64> imm;
282  bits<4> pseudo;
283
284  let Inst{63-61} = mode;
285  let Inst{60-59} = size;
286  let Inst{51-48} = dst;
287  let Inst{55-52} = pseudo;
288  let Inst{47-32} = 0;
289  let Inst{31-0} = imm{31-0};
290
291  let mode = 0;     // BPF_IMM
292  let size = 3;     // BPF_DW
293  let BPFClass = 0; // BPF_LD
294}
295
296// STORE instructions
297class STORE<bits<2> SizeOp, string OpcodeStr, list<dag> Pattern>
298    : InstBPF<(outs), (ins GPR:$src, MEMri:$addr),
299              !strconcat(OpcodeStr, "\t$addr, $src"), Pattern> {
300  bits<3> mode;
301  bits<2> size;
302  bits<4> src;
303  bits<20> addr;
304
305  let Inst{63-61} = mode;
306  let Inst{60-59} = size;
307  let Inst{51-48} = addr{19-16}; // base reg
308  let Inst{55-52} = src;
309  let Inst{47-32} = addr{15-0}; // offset
310
311  let mode = 3;     // BPF_MEM
312  let size = SizeOp;
313  let BPFClass = 3; // BPF_STX
314}
315
316class STOREi64<bits<2> Opc, string OpcodeStr, PatFrag OpNode>
317    : STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;
318
319def STW : STOREi64<0x0, "stw", truncstorei32>;
320def STH : STOREi64<0x1, "sth", truncstorei16>;
321def STB : STOREi64<0x2, "stb", truncstorei8>;
322def STD : STOREi64<0x3, "std", store>;
323
324// LOAD instructions
325class LOAD<bits<2> SizeOp, string OpcodeStr, list<dag> Pattern>
326    : InstBPF<(outs GPR:$dst), (ins MEMri:$addr),
327              !strconcat(OpcodeStr, "\t$dst, $addr"), Pattern> {
328  bits<3> mode;
329  bits<2> size;
330  bits<4> dst;
331  bits<20> addr;
332
333  let Inst{63-61} = mode;
334  let Inst{60-59} = size;
335  let Inst{51-48} = dst;
336  let Inst{55-52} = addr{19-16};
337  let Inst{47-32} = addr{15-0};
338
339  let mode = 3;     // BPF_MEM
340  let size = SizeOp;
341  let BPFClass = 1; // BPF_LDX
342}
343
344class LOADi64<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
345    : LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>;
346
347def LDW : LOADi64<0x0, "ldw", zextloadi32>;
348def LDH : LOADi64<0x1, "ldh", zextloadi16>;
349def LDB : LOADi64<0x2, "ldb", zextloadi8>;
350def LDD : LOADi64<0x3, "ldd", load>;
351
352class BRANCH<bits<4> Opc, string OpcodeStr, list<dag> Pattern>
353    : InstBPF<(outs), (ins brtarget:$BrDst),
354              !strconcat(OpcodeStr, "\t$BrDst"), Pattern> {
355  bits<4> op;
356  bits<16> BrDst;
357  bits<1> BPFSrc;
358
359  let Inst{63-60} = op;
360  let Inst{59} = BPFSrc;
361  let Inst{47-32} = BrDst;
362
363  let op = Opc;
364  let BPFSrc = 0;
365  let BPFClass = 5; // BPF_JMP
366}
367
368class CALL<string OpcodeStr>
369    : InstBPF<(outs), (ins calltarget:$BrDst),
370              !strconcat(OpcodeStr, "\t$BrDst"), []> {
371  bits<4> op;
372  bits<32> BrDst;
373  bits<1> BPFSrc;
374
375  let Inst{63-60} = op;
376  let Inst{59} = BPFSrc;
377  let Inst{31-0} = BrDst;
378
379  let op = 8;       // BPF_CALL
380  let BPFSrc = 0;
381  let BPFClass = 5; // BPF_JMP
382}
383
384// Jump always
385let isBranch = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1 in {
386  def JMP : BRANCH<0x0, "jmp", [(br bb:$BrDst)]>;
387}
388
389// Jump and link
390let isCall=1, hasDelaySlot=0, Uses = [R11],
391    // Potentially clobbered registers
392    Defs = [R0, R1, R2, R3, R4, R5] in {
393  def JAL  : CALL<"call">;
394}
395
396class NOP_I<string OpcodeStr>
397    : InstBPF<(outs), (ins i32imm:$imm),
398              !strconcat(OpcodeStr, "\t$imm"), []> {
399  // mov r0, r0 == nop
400  bits<4> op;
401  bits<1> BPFSrc;
402  bits<4> dst;
403  bits<4> src;
404
405  let Inst{63-60} = op;
406  let Inst{59} = BPFSrc;
407  let Inst{55-52} = src;
408  let Inst{51-48} = dst;
409
410  let op = 0xb;     // BPF_MOV
411  let BPFSrc = 1;   // BPF_X
412  let BPFClass = 7; // BPF_ALU64
413  let src = 0;      // R0
414  let dst = 0;      // R0
415}
416
417let hasSideEffects = 0 in
418  def NOP : NOP_I<"nop">;
419
420class RET<string OpcodeStr>
421    : InstBPF<(outs), (ins),
422              !strconcat(OpcodeStr, ""), [(BPFretflag)]> {
423  bits<4> op;
424
425  let Inst{63-60} = op;
426  let Inst{59} = 0;
427  let Inst{31-0} = 0;
428
429  let op = 9;       // BPF_EXIT
430  let BPFClass = 5; // BPF_JMP
431}
432
433let isReturn = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1,
434    isNotDuplicable = 1 in {
435  def RET : RET<"ret">;
436}
437
438// ADJCALLSTACKDOWN/UP pseudo insns
439let Defs = [R11], Uses = [R11] in {
440def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
441                              "#ADJCALLSTACKDOWN $amt",
442                              [(BPFcallseq_start timm:$amt)]>;
443def ADJCALLSTACKUP   : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
444                              "#ADJCALLSTACKUP $amt1 $amt2",
445                              [(BPFcallseq_end timm:$amt1, timm:$amt2)]>;
446}
447
448let usesCustomInserter = 1 in {
449  def Select : Pseudo<(outs GPR:$dst),
450                      (ins GPR:$lhs, GPR:$rhs, i64imm:$imm, GPR:$src, GPR:$src2),
451                      "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2",
452                      [(set i64:$dst,
453                       (BPFselectcc i64:$lhs, i64:$rhs, (i64 imm:$imm), i64:$src, i64:$src2))]>;
454}
455
456// load 64-bit global addr into register
457def : Pat<(BPFWrapper tglobaladdr:$in), (LD_imm64 tglobaladdr:$in)>;
458
459// 0xffffFFFF doesn't fit into simm32, optimize common case
460def : Pat<(i64 (and (i64 GPR:$src), 0xffffFFFF)),
461          (SRL_ri (SLL_ri (i64 GPR:$src), 32), 32)>;
462
463// Calls
464def : Pat<(BPFcall tglobaladdr:$dst), (JAL tglobaladdr:$dst)>;
465def : Pat<(BPFcall imm:$dst), (JAL imm:$dst)>;
466
467// Loads
468def : Pat<(extloadi8  ADDRri:$src), (i64 (LDB ADDRri:$src))>;
469def : Pat<(extloadi16 ADDRri:$src), (i64 (LDH ADDRri:$src))>;
470def : Pat<(extloadi32 ADDRri:$src), (i64 (LDW ADDRri:$src))>;
471
472// Atomics
473class XADD<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
474    : InstBPF<(outs GPR:$dst), (ins MEMri:$addr, GPR:$val),
475              !strconcat(OpcodeStr, "\t$dst, $addr, $val"),
476              [(set GPR:$dst, (OpNode ADDRri:$addr, GPR:$val))]> {
477  bits<3> mode;
478  bits<2> size;
479  bits<4> src;
480  bits<20> addr;
481
482  let Inst{63-61} = mode;
483  let Inst{60-59} = size;
484  let Inst{51-48} = addr{19-16}; // base reg
485  let Inst{55-52} = src;
486  let Inst{47-32} = addr{15-0}; // offset
487
488  let mode = 6;     // BPF_XADD
489  let size = SizeOp;
490  let BPFClass = 3; // BPF_STX
491}
492
493let Constraints = "$dst = $val" in {
494def XADD32 : XADD<0, "xadd32", atomic_load_add_32>;
495def XADD64 : XADD<3, "xadd64", atomic_load_add_64>;
496// undefined def XADD16 : XADD<1, "xadd16", atomic_load_add_16>;
497// undefined def XADD8  : XADD<2, "xadd8", atomic_load_add_8>;
498}
499
500// bswap16, bswap32, bswap64
501class BSWAP<bits<32> SizeOp, string OpcodeStr, list<dag> Pattern>
502    : InstBPF<(outs GPR:$dst), (ins GPR:$src),
503              !strconcat(OpcodeStr, "\t$dst"),
504              Pattern> {
505  bits<4> op;
506  bits<1> BPFSrc;
507  bits<4> dst;
508  bits<32> imm;
509
510  let Inst{63-60} = op;
511  let Inst{59} = BPFSrc;
512  let Inst{51-48} = dst;
513  let Inst{31-0} = imm;
514
515  let op = 0xd;     // BPF_END
516  let BPFSrc = 1;   // BPF_TO_BE (TODO: use BPF_TO_LE for big-endian target)
517  let BPFClass = 4; // BPF_ALU
518  let imm = SizeOp;
519}
520
521let Constraints = "$dst = $src" in {
522def BSWAP16 : BSWAP<16, "bswap16", [(set GPR:$dst, (srl (bswap GPR:$src), (i64 48)))]>;
523def BSWAP32 : BSWAP<32, "bswap32", [(set GPR:$dst, (srl (bswap GPR:$src), (i64 32)))]>;
524def BSWAP64 : BSWAP<64, "bswap64", [(set GPR:$dst, (bswap GPR:$src))]>;
525}
526
527let Defs = [R0, R1, R2, R3, R4, R5], Uses = [R6], hasSideEffects = 1,
528    hasExtraDefRegAllocReq = 1, hasExtraSrcRegAllocReq = 1, mayLoad = 1 in {
529class LOAD_ABS<bits<2> SizeOp, string OpcodeStr, Intrinsic OpNode>
530    : InstBPF<(outs), (ins GPR:$skb, i64imm:$imm),
531              !strconcat(OpcodeStr, "\tr0, $skb.data + $imm"),
532              [(set R0, (OpNode GPR:$skb, i64immSExt32:$imm))]> {
533  bits<3> mode;
534  bits<2> size;
535  bits<32> imm;
536
537  let Inst{63-61} = mode;
538  let Inst{60-59} = size;
539  let Inst{31-0} = imm;
540
541  let mode = 1;     // BPF_ABS
542  let size = SizeOp;
543  let BPFClass = 0; // BPF_LD
544}
545
546class LOAD_IND<bits<2> SizeOp, string OpcodeStr, Intrinsic OpNode>
547    : InstBPF<(outs), (ins GPR:$skb, GPR:$val),
548              !strconcat(OpcodeStr, "\tr0, $skb.data + $val"),
549              [(set R0, (OpNode GPR:$skb, GPR:$val))]> {
550  bits<3> mode;
551  bits<2> size;
552  bits<4> val;
553
554  let Inst{63-61} = mode;
555  let Inst{60-59} = size;
556  let Inst{55-52} = val;
557
558  let mode = 2;     // BPF_IND
559  let size = SizeOp;
560  let BPFClass = 0; // BPF_LD
561}
562}
563
564def LD_ABS_B : LOAD_ABS<2, "ldabs_b", int_bpf_load_byte>;
565def LD_ABS_H : LOAD_ABS<1, "ldabs_h", int_bpf_load_half>;
566def LD_ABS_W : LOAD_ABS<0, "ldabs_w", int_bpf_load_word>;
567
568def LD_IND_B : LOAD_IND<2, "ldind_b", int_bpf_load_byte>;
569def LD_IND_H : LOAD_IND<1, "ldind_h", int_bpf_load_half>;
570def LD_IND_W : LOAD_IND<0, "ldind_w", int_bpf_load_word>;
571