| /external/mesa3d/src/gallium/drivers/nouveau/nv50/ |
| D | nv50_formats.c | 167 I3(A, L8_SINT, R8_SINT, R, R, R, xx, SINT, R8, TR),
172 I3(A, L16_SINT, R16_SINT, R, R, R, xx, SINT, R16, TR),
175 I3(A, L32_SINT, R32_SINT, R, R, R, xx, SINT, R32, TR),
180 C4(A, I8_SINT, R8_SINT, R, R, R, R, SINT, R8, TR),
185 C4(A, I16_SINT, R16_SINT, R, R, R, R, SINT, R16, TR),
188 C4(A, I32_SINT, R32_SINT, R, R, R, R, SINT, R32, TR),
193 A1(A, A8_SINT, R8_SINT, xx, xx, xx, R, SINT, R8, T),
198 A1(A, A16_SINT, R16_SINT, xx, xx, xx, R, SINT, R16, T),
201 A1(A, A32_SINT, R32_SINT, xx, xx, xx, R, SINT, R32, T),
208 C4(A, L8A8_SINT, RG8_SINT, R, R, R, G, SINT, G8R8, T),
[all …]
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| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir.cpp | 990 { "RGBA32I", 4, { 32, 32, 32, 32 }, SINT },
991 { "RGBA16I", 4, { 16, 16, 16, 16 }, SINT },
992 { "RGBA8I", 4, { 8, 8, 8, 8 }, SINT },
993 { "RG32I", 2, { 32, 32, 0, 0 }, SINT },
994 { "RG16I", 2, { 16, 16, 0, 0 }, SINT },
995 { "RG8I", 2, { 8, 8, 0, 0 }, SINT },
996 { "R32I", 1, { 32, 0, 0, 0 }, SINT },
997 { "R16I", 1, { 16, 0, 0, 0 }, SINT },
998 { "R8I", 1, { 8, 0, 0, 0 }, SINT },
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| D | nv50_ir.h | 423 SINT, enumerator
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| D | nv50_ir_lowering_nvc0.cpp | 1901 case SINT: in getSrcType()
1917 case SINT: in getDestType()
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| /external/mesa3d/src/gallium/docs/source/ |
| D | format.rst | 20 - ``SINT``: N bit signed integer [-2^(N-1) ... 2^(N-1) - 1]
30 The difference between ``SINT`` and ``SSCALED`` is that the former are pure
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| D | tgsi.rst | 3374 level) out of UNORM, SNORM, SINT, UINT and FLOAT.
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| /external/syslinux/gpxe/src/drivers/net/ |
| D | amd8111e.h | 177 SINT = (1 << 12), enumerator
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 6665 SDValue SINT = Op.getOperand(0); in LowerINT_TO_FP() local
6687 SINT, DAG.getConstant(2047, dl, MVT::i64)); in LowerINT_TO_FP()
6690 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT); in LowerINT_TO_FP()
6703 SINT, DAG.getConstant(53, dl, MVT::i32)); in LowerINT_TO_FP()
6709 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT); in LowerINT_TO_FP()
6716 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) { in LowerINT_TO_FP()
6722 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) { in LowerINT_TO_FP()
6732 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) { in LowerINT_TO_FP()
6742 SINT.getOpcode() == ISD::SIGN_EXTEND) || in LowerINT_TO_FP()
6744 SINT.getOpcode() == ISD::ZERO_EXTEND)) && in LowerINT_TO_FP()
[all …]
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| /external/mesa3d/src/gallium/drivers/nouveau/nvc0/ |
| D | nvc0_vbo.c | 189 mode = VTX_ATTR(a, 4, SINT, 32); in nvc0_set_constant_vertex_attrib()
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| /external/vulkan-validation-layers/layers/ |
| D | vk_validation_layer_details.md | 141 …the basic component type must match (float for UNORM/SNORM/FLOAT, int for SINT, uint for UINT) as …
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