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Searched refs:SPL (Results 1 – 25 of 27) sorted by relevance

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/external/libunwind/tests/
DGia64-test-rbs.c71 #define SPL(n) rbs_spill_##n macro
74 SPL(2), SPL(3), SPL(4), SPL(5), SPL(6), SPL(7),
75 SPL(8), SPL(9), SPL(10), SPL(11), SPL(12), SPL(13), SPL(14), SPL(15),
76 SPL(16), SPL(17), SPL(18), SPL(19), SPL(20), SPL(21), SPL(22), SPL(23),
77 SPL(24), SPL(25), SPL(26), SPL(27), SPL(28), SPL(29), SPL(30), SPL(31),
78 SPL(32), SPL(33), SPL(34), SPL(35), SPL(36), SPL(37), SPL(38), SPL(39),
79 SPL(40), SPL(41), SPL(42), SPL(43), SPL(44), SPL(45), SPL(46), SPL(47),
80 SPL(48), SPL(49), SPL(50), SPL(51), SPL(52), SPL(53), SPL(54), SPL(55),
81 SPL(56), SPL(57), SPL(58), SPL(59), SPL(60), SPL(61), SPL(62), SPL(63),
82 SPL(64), SPL(65), SPL(66), SPL(67), SPL(68), SPL(69), SPL(70), SPL(71),
[all …]
/external/llvm/test/CodeGen/NVPTX/
Dlocal-stack-frame.ll6 ; PTX32: mov.u32 %SPL, __local_depot{{[0-9]+}};
7 ; PTX32: cvta.local.u32 %SP, %SPL;
10 ; PTX64: mov.u64 %SPL, __local_depot{{[0-9]+}};
11 ; PTX64: cvta.local.u64 %SP, %SPL;
20 ; PTX32: mov.u32 %SPL, __local_depot{{[0-9]+}};
21 ; PTX32: cvta.local.u32 %SP, %SPL;
23 ; PTX32: add.u32 %r[[SP_REG:[0-9]+]], %SPL, 0;
25 ; PTX64: mov.u64 %SPL, __local_depot{{[0-9]+}};
26 ; PTX64: cvta.local.u64 %SP, %SPL;
28 ; PTX64: add.u64 %rd[[SP_REG:[0-9]+]], %SPL, 0;
[all …]
Dcall-with-alloca-buffer.ll23 ; CHECK: mov.u64 %SPL
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp108 X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::RAX, X86::RBX, in initLLVMToSEHAndCVRegMapping()
291 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
319 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
320 return X86::SPL; in getX86SubSuperRegisterOrZero()
356 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
392 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
428 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
DX86BaseInfo.h761 return (reg == X86::SPL || reg == X86::BPL || in isX86_64NonExtLowByteReg()
/external/vboot_reference/tests/futility/
Ddata_fmap2_expect_hh.txt26 BL2 SPL 00002000 00006000 00004000
Ddata_fmap2_expect_hhH.txt31 BL2 SPL 00002000 00006000 00004000
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86RegisterInfo.cpp397 Reserved.set(X86::SPL); in getReservedRegs()
427 Reserved.set(X86::SPL); in getReservedRegs()
695 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegister()
696 return X86::SPL; in getX86SubSuperRegister()
732 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegister()
768 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegister()
804 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegister()
DX86RegisterInfo.td54 def SPL : Register<"spl">;
83 def SP : RegisterWithSubRegs<"sp", [SPL]>;
279 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
289 (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
DX86GenRegisterInfo.inc137 SPL = 118,
302 const unsigned ESP_Overlaps[] = { X86::ESP, X86::RSP, X86::SP, X86::SPL, 0 };
362 const unsigned RSP_Overlaps[] = { X86::RSP, X86::ESP, X86::SP, X86::SPL, 0 };
365 const unsigned SP_Overlaps[] = { X86::SP, X86::ESP, X86::RSP, X86::SPL, 0 };
366 const unsigned SPL_Overlaps[] = { X86::SPL, X86::ESP, X86::RSP, X86::SP, 0 };
423 const unsigned ESP_SubRegsSet[] = { X86::SP, X86::SPL, 0 };
456 const unsigned RSP_SubRegsSet[] = { X86::ESP, X86::SP, X86::SPL, 0 };
458 const unsigned SP_SubRegsSet[] = { X86::SPL, 0 };
683 { "SPL", SPL_Overlaps, Empty_SubRegsSet, SPL_SuperRegsSet },
730 …AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B…
[all …]
DX86GenAsmWriter.inc6534 case X86::SPL:
/external/llvm/lib/Target/AVR/
DAVRRegisterInfo.td77 def SPL : AVRReg<32, "SPL">, DwarfRegNum<[32]>;
84 def SP : AVRReg<32, "SP", [SPL, SPH]>, DwarfRegNum<[32]>;
DAVRRegisterInfo.cpp64 Reserved.set(AVR::SPL); in getReservedRegs()
/external/llvm/lib/Target/NVPTX/
DNVPTXRegisterInfo.td27 def VRFrameLocal : NVPTXReg<"%SPL">;
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h541 return (reg == X86::SPL || reg == X86::BPL || in isX86_64NonExtLowByteReg()
DX86MCTargetDesc.cpp149 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH: in getX86RegNum()
/external/llvm/lib/Target/X86/
DX86RegisterInfo.td65 def SPL : X86Reg<"spl", 4>;
87 def SP : X86Reg<"sp", 4, [SPL]>;
319 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
329 (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
DX86RegisterInfo.cpp487 Reserved.set(X86::SPL); in getReservedRegs()
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinRegisterInfo.td121 def SP : Rii<1, 6, "sp", [SPH, SPL]>, DwarfRegNum<[14]>;
205 (add (sequence "P%uL", 0, 5), SPL, FPL)>;
/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h83 ENTRY(SPL) \
/external/curl/docs/
DBINDINGS.md92 [SPL](http://www.clifford.at/spl/) Written by Clifford Wolf
DFAQ603 Scheme, S-Lang, Smalltalk, SP-Forth, SPL, Tcl, Visual Basic, Visual FoxPro,
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h93 ENTRY(SPL) \
/external/llvm/docs/TableGen/
Dindex.rst68 RDX, RIP, RSI, RSP, SI, SIL, SP, SPL, ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
/external/lisa/ipynb/examples/energy_meter/
DEnergyMeter_Monsoon.ipynb634 …zy3O6+tLu/mOSfkjxueM8nktx7GMp7+ySvHtZ3TXLXJJ+sqsokxD6zuy/o7h8n+csk\nj5469y+SPL+7f9rdl2yhvgOGHthf/i…

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