1//===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the X86 Register file, defining the registers themselves, 11// aliases between the registers, and the register classes built out of the 12// registers. 13// 14//===----------------------------------------------------------------------===// 15 16//===----------------------------------------------------------------------===// 17// Register definitions... 18// 19let Namespace = "X86" in { 20 21 // Subregister indices. 22 def sub_8bit : SubRegIndex; 23 def sub_8bit_hi : SubRegIndex; 24 def sub_16bit : SubRegIndex; 25 def sub_32bit : SubRegIndex; 26 27 def sub_ss : SubRegIndex; 28 def sub_sd : SubRegIndex; 29 def sub_xmm : SubRegIndex; 30 31 32 // In the register alias definitions below, we define which registers alias 33 // which others. We only specify which registers the small registers alias, 34 // because the register file generator is smart enough to figure out that 35 // AL aliases AX if we tell it that AX aliased AL (for example). 36 37 // Dwarf numbering is different for 32-bit and 64-bit, and there are 38 // variations by target as well. Currently the first entry is for X86-64, 39 // second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux 40 // and debug information on X86-32/Darwin) 41 42 // 8-bit registers 43 // Low registers 44 def AL : Register<"al">; 45 def DL : Register<"dl">; 46 def CL : Register<"cl">; 47 def BL : Register<"bl">; 48 49 // X86-64 only, requires REX. 50 let CostPerUse = 1 in { 51 def SIL : Register<"sil">; 52 def DIL : Register<"dil">; 53 def BPL : Register<"bpl">; 54 def SPL : Register<"spl">; 55 def R8B : Register<"r8b">; 56 def R9B : Register<"r9b">; 57 def R10B : Register<"r10b">; 58 def R11B : Register<"r11b">; 59 def R12B : Register<"r12b">; 60 def R13B : Register<"r13b">; 61 def R14B : Register<"r14b">; 62 def R15B : Register<"r15b">; 63 } 64 65 // High registers. On x86-64, these cannot be used in any instruction 66 // with a REX prefix. 67 def AH : Register<"ah">; 68 def DH : Register<"dh">; 69 def CH : Register<"ch">; 70 def BH : Register<"bh">; 71 72 // 16-bit registers 73 let SubRegIndices = [sub_8bit, sub_8bit_hi] in { 74 def AX : RegisterWithSubRegs<"ax", [AL,AH]>; 75 def DX : RegisterWithSubRegs<"dx", [DL,DH]>; 76 def CX : RegisterWithSubRegs<"cx", [CL,CH]>; 77 def BX : RegisterWithSubRegs<"bx", [BL,BH]>; 78 } 79 let SubRegIndices = [sub_8bit] in { 80 def SI : RegisterWithSubRegs<"si", [SIL]>; 81 def DI : RegisterWithSubRegs<"di", [DIL]>; 82 def BP : RegisterWithSubRegs<"bp", [BPL]>; 83 def SP : RegisterWithSubRegs<"sp", [SPL]>; 84 } 85 def IP : Register<"ip">; 86 87 // X86-64 only, requires REX. 88 let SubRegIndices = [sub_8bit], CostPerUse = 1 in { 89 def R8W : RegisterWithSubRegs<"r8w", [R8B]>; 90 def R9W : RegisterWithSubRegs<"r9w", [R9B]>; 91 def R10W : RegisterWithSubRegs<"r10w", [R10B]>; 92 def R11W : RegisterWithSubRegs<"r11w", [R11B]>; 93 def R12W : RegisterWithSubRegs<"r12w", [R12B]>; 94 def R13W : RegisterWithSubRegs<"r13w", [R13B]>; 95 def R14W : RegisterWithSubRegs<"r14w", [R14B]>; 96 def R15W : RegisterWithSubRegs<"r15w", [R15B]>; 97 } 98 // 32-bit registers 99 let SubRegIndices = [sub_16bit] in { 100 def EAX : RegisterWithSubRegs<"eax", [AX]>, DwarfRegNum<[-2, 0, 0]>; 101 def EDX : RegisterWithSubRegs<"edx", [DX]>, DwarfRegNum<[-2, 2, 2]>; 102 def ECX : RegisterWithSubRegs<"ecx", [CX]>, DwarfRegNum<[-2, 1, 1]>; 103 def EBX : RegisterWithSubRegs<"ebx", [BX]>, DwarfRegNum<[-2, 3, 3]>; 104 def ESI : RegisterWithSubRegs<"esi", [SI]>, DwarfRegNum<[-2, 6, 6]>; 105 def EDI : RegisterWithSubRegs<"edi", [DI]>, DwarfRegNum<[-2, 7, 7]>; 106 def EBP : RegisterWithSubRegs<"ebp", [BP]>, DwarfRegNum<[-2, 4, 5]>; 107 def ESP : RegisterWithSubRegs<"esp", [SP]>, DwarfRegNum<[-2, 5, 4]>; 108 def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[-2, 8, 8]>; 109 110 // X86-64 only, requires REX 111 let CostPerUse = 1 in { 112 def R8D : RegisterWithSubRegs<"r8d", [R8W]>; 113 def R9D : RegisterWithSubRegs<"r9d", [R9W]>; 114 def R10D : RegisterWithSubRegs<"r10d", [R10W]>; 115 def R11D : RegisterWithSubRegs<"r11d", [R11W]>; 116 def R12D : RegisterWithSubRegs<"r12d", [R12W]>; 117 def R13D : RegisterWithSubRegs<"r13d", [R13W]>; 118 def R14D : RegisterWithSubRegs<"r14d", [R14W]>; 119 def R15D : RegisterWithSubRegs<"r15d", [R15W]>; 120 }} 121 122 // 64-bit registers, X86-64 only 123 let SubRegIndices = [sub_32bit] in { 124 def RAX : RegisterWithSubRegs<"rax", [EAX]>, DwarfRegNum<[0, -2, -2]>; 125 def RDX : RegisterWithSubRegs<"rdx", [EDX]>, DwarfRegNum<[1, -2, -2]>; 126 def RCX : RegisterWithSubRegs<"rcx", [ECX]>, DwarfRegNum<[2, -2, -2]>; 127 def RBX : RegisterWithSubRegs<"rbx", [EBX]>, DwarfRegNum<[3, -2, -2]>; 128 def RSI : RegisterWithSubRegs<"rsi", [ESI]>, DwarfRegNum<[4, -2, -2]>; 129 def RDI : RegisterWithSubRegs<"rdi", [EDI]>, DwarfRegNum<[5, -2, -2]>; 130 def RBP : RegisterWithSubRegs<"rbp", [EBP]>, DwarfRegNum<[6, -2, -2]>; 131 def RSP : RegisterWithSubRegs<"rsp", [ESP]>, DwarfRegNum<[7, -2, -2]>; 132 133 // These also require REX. 134 let CostPerUse = 1 in { 135 def R8 : RegisterWithSubRegs<"r8", [R8D]>, DwarfRegNum<[8, -2, -2]>; 136 def R9 : RegisterWithSubRegs<"r9", [R9D]>, DwarfRegNum<[9, -2, -2]>; 137 def R10 : RegisterWithSubRegs<"r10", [R10D]>, DwarfRegNum<[10, -2, -2]>; 138 def R11 : RegisterWithSubRegs<"r11", [R11D]>, DwarfRegNum<[11, -2, -2]>; 139 def R12 : RegisterWithSubRegs<"r12", [R12D]>, DwarfRegNum<[12, -2, -2]>; 140 def R13 : RegisterWithSubRegs<"r13", [R13D]>, DwarfRegNum<[13, -2, -2]>; 141 def R14 : RegisterWithSubRegs<"r14", [R14D]>, DwarfRegNum<[14, -2, -2]>; 142 def R15 : RegisterWithSubRegs<"r15", [R15D]>, DwarfRegNum<[15, -2, -2]>; 143 def RIP : RegisterWithSubRegs<"rip", [EIP]>, DwarfRegNum<[16, -2, -2]>; 144 }} 145 146 // MMX Registers. These are actually aliased to ST0 .. ST7 147 def MM0 : Register<"mm0">, DwarfRegNum<[41, 29, 29]>; 148 def MM1 : Register<"mm1">, DwarfRegNum<[42, 30, 30]>; 149 def MM2 : Register<"mm2">, DwarfRegNum<[43, 31, 31]>; 150 def MM3 : Register<"mm3">, DwarfRegNum<[44, 32, 32]>; 151 def MM4 : Register<"mm4">, DwarfRegNum<[45, 33, 33]>; 152 def MM5 : Register<"mm5">, DwarfRegNum<[46, 34, 34]>; 153 def MM6 : Register<"mm6">, DwarfRegNum<[47, 35, 35]>; 154 def MM7 : Register<"mm7">, DwarfRegNum<[48, 36, 36]>; 155 156 // Pseudo Floating Point registers 157 def FP0 : Register<"fp0">; 158 def FP1 : Register<"fp1">; 159 def FP2 : Register<"fp2">; 160 def FP3 : Register<"fp3">; 161 def FP4 : Register<"fp4">; 162 def FP5 : Register<"fp5">; 163 def FP6 : Register<"fp6">; 164 165 // XMM Registers, used by the various SSE instruction set extensions. 166 // The sub_ss and sub_sd subregs are the same registers with another regclass. 167 let CompositeIndices = [(sub_ss), (sub_sd)] in { 168 def XMM0: Register<"xmm0">, DwarfRegNum<[17, 21, 21]>; 169 def XMM1: Register<"xmm1">, DwarfRegNum<[18, 22, 22]>; 170 def XMM2: Register<"xmm2">, DwarfRegNum<[19, 23, 23]>; 171 def XMM3: Register<"xmm3">, DwarfRegNum<[20, 24, 24]>; 172 def XMM4: Register<"xmm4">, DwarfRegNum<[21, 25, 25]>; 173 def XMM5: Register<"xmm5">, DwarfRegNum<[22, 26, 26]>; 174 def XMM6: Register<"xmm6">, DwarfRegNum<[23, 27, 27]>; 175 def XMM7: Register<"xmm7">, DwarfRegNum<[24, 28, 28]>; 176 177 // X86-64 only 178 let CostPerUse = 1 in { 179 def XMM8: Register<"xmm8">, DwarfRegNum<[25, -2, -2]>; 180 def XMM9: Register<"xmm9">, DwarfRegNum<[26, -2, -2]>; 181 def XMM10: Register<"xmm10">, DwarfRegNum<[27, -2, -2]>; 182 def XMM11: Register<"xmm11">, DwarfRegNum<[28, -2, -2]>; 183 def XMM12: Register<"xmm12">, DwarfRegNum<[29, -2, -2]>; 184 def XMM13: Register<"xmm13">, DwarfRegNum<[30, -2, -2]>; 185 def XMM14: Register<"xmm14">, DwarfRegNum<[31, -2, -2]>; 186 def XMM15: Register<"xmm15">, DwarfRegNum<[32, -2, -2]>; 187 }} 188 189 // YMM Registers, used by AVX instructions 190 let SubRegIndices = [sub_xmm] in { 191 def YMM0: RegisterWithSubRegs<"ymm0", [XMM0]>, DwarfRegAlias<XMM0>; 192 def YMM1: RegisterWithSubRegs<"ymm1", [XMM1]>, DwarfRegAlias<XMM1>; 193 def YMM2: RegisterWithSubRegs<"ymm2", [XMM2]>, DwarfRegAlias<XMM2>; 194 def YMM3: RegisterWithSubRegs<"ymm3", [XMM3]>, DwarfRegAlias<XMM3>; 195 def YMM4: RegisterWithSubRegs<"ymm4", [XMM4]>, DwarfRegAlias<XMM4>; 196 def YMM5: RegisterWithSubRegs<"ymm5", [XMM5]>, DwarfRegAlias<XMM5>; 197 def YMM6: RegisterWithSubRegs<"ymm6", [XMM6]>, DwarfRegAlias<XMM6>; 198 def YMM7: RegisterWithSubRegs<"ymm7", [XMM7]>, DwarfRegAlias<XMM7>; 199 def YMM8: RegisterWithSubRegs<"ymm8", [XMM8]>, DwarfRegAlias<XMM8>; 200 def YMM9: RegisterWithSubRegs<"ymm9", [XMM9]>, DwarfRegAlias<XMM9>; 201 def YMM10: RegisterWithSubRegs<"ymm10", [XMM10]>, DwarfRegAlias<XMM10>; 202 def YMM11: RegisterWithSubRegs<"ymm11", [XMM11]>, DwarfRegAlias<XMM11>; 203 def YMM12: RegisterWithSubRegs<"ymm12", [XMM12]>, DwarfRegAlias<XMM12>; 204 def YMM13: RegisterWithSubRegs<"ymm13", [XMM13]>, DwarfRegAlias<XMM13>; 205 def YMM14: RegisterWithSubRegs<"ymm14", [XMM14]>, DwarfRegAlias<XMM14>; 206 def YMM15: RegisterWithSubRegs<"ymm15", [XMM15]>, DwarfRegAlias<XMM15>; 207 } 208 209 class STRegister<string Name, list<Register> A> : Register<Name> { 210 let Aliases = A; 211 } 212 213 // Floating point stack registers. These don't map one-to-one to the FP 214 // pseudo registers, but we still mark them as aliasing FP registers. That 215 // way both kinds can be live without exceeding the stack depth. ST registers 216 // are only live around inline assembly. 217 def ST0 : STRegister<"st(0)", []>, DwarfRegNum<[33, 12, 11]>; 218 def ST1 : STRegister<"st(1)", [FP6]>, DwarfRegNum<[34, 13, 12]>; 219 def ST2 : STRegister<"st(2)", [FP5]>, DwarfRegNum<[35, 14, 13]>; 220 def ST3 : STRegister<"st(3)", [FP4]>, DwarfRegNum<[36, 15, 14]>; 221 def ST4 : STRegister<"st(4)", [FP3]>, DwarfRegNum<[37, 16, 15]>; 222 def ST5 : STRegister<"st(5)", [FP2]>, DwarfRegNum<[38, 17, 16]>; 223 def ST6 : STRegister<"st(6)", [FP1]>, DwarfRegNum<[39, 18, 17]>; 224 def ST7 : STRegister<"st(7)", [FP0]>, DwarfRegNum<[40, 19, 18]>; 225 226 // Status flags register 227 def EFLAGS : Register<"flags">; 228 229 // Segment registers 230 def CS : Register<"cs">; 231 def DS : Register<"ds">; 232 def SS : Register<"ss">; 233 def ES : Register<"es">; 234 def FS : Register<"fs">; 235 def GS : Register<"gs">; 236 237 // Debug registers 238 def DR0 : Register<"dr0">; 239 def DR1 : Register<"dr1">; 240 def DR2 : Register<"dr2">; 241 def DR3 : Register<"dr3">; 242 def DR4 : Register<"dr4">; 243 def DR5 : Register<"dr5">; 244 def DR6 : Register<"dr6">; 245 def DR7 : Register<"dr7">; 246 247 // Control registers 248 def CR0 : Register<"cr0">; 249 def CR1 : Register<"cr1">; 250 def CR2 : Register<"cr2">; 251 def CR3 : Register<"cr3">; 252 def CR4 : Register<"cr4">; 253 def CR5 : Register<"cr5">; 254 def CR6 : Register<"cr6">; 255 def CR7 : Register<"cr7">; 256 def CR8 : Register<"cr8">; 257 def CR9 : Register<"cr9">; 258 def CR10 : Register<"cr10">; 259 def CR11 : Register<"cr11">; 260 def CR12 : Register<"cr12">; 261 def CR13 : Register<"cr13">; 262 def CR14 : Register<"cr14">; 263 def CR15 : Register<"cr15">; 264 265 // Pseudo index registers 266 def EIZ : Register<"eiz">; 267 def RIZ : Register<"riz">; 268} 269 270 271//===----------------------------------------------------------------------===// 272// Register Class Definitions... now that we have all of the pieces, define the 273// top-level register classes. The order specified in the register list is 274// implicitly defined to be the register allocation order. 275// 276 277// List call-clobbered registers before callee-save registers. RBX, RBP, (and 278// R12, R13, R14, and R15 for X86-64) are callee-save registers. 279// In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and 280// R8B, ... R15B. 281// Allocate R12 and R13 last, as these require an extra byte when 282// encoded in x86_64 instructions. 283// FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in 284// 64-bit mode. The main complication is that they cannot be encoded in an 285// instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc. 286// require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d" 287// cannot be encoded. 288def GR8 : RegisterClass<"X86", [i8], 8, 289 (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL, 290 R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B)> { 291 let AltOrders = [(sub GR8, AH, BH, CH, DH)]; 292 let AltOrderSelect = [{ 293 return MF.getTarget().getSubtarget<X86Subtarget>().is64Bit(); 294 }]; 295} 296 297def GR16 : RegisterClass<"X86", [i16], 16, 298 (add AX, CX, DX, SI, DI, BX, BP, SP, 299 R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W)> { 300 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi)]; 301} 302 303def GR32 : RegisterClass<"X86", [i32], 32, 304 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP, 305 R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D)> { 306 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)]; 307} 308 309// GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since 310// RIP isn't really a register and it can't be used anywhere except in an 311// address, but it doesn't cause trouble. 312def GR64 : RegisterClass<"X86", [i64], 64, 313 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 314 RBX, R14, R15, R12, R13, RBP, RSP, RIP)> { 315 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), 316 (GR16 sub_16bit), 317 (GR32 sub_32bit)]; 318} 319 320// Segment registers for use by MOV instructions (and others) that have a 321// segment register as one operand. Always contain a 16-bit segment 322// descriptor. 323def SEGMENT_REG : RegisterClass<"X86", [i16], 16, (add CS, DS, SS, ES, FS, GS)>; 324 325// Debug registers. 326def DEBUG_REG : RegisterClass<"X86", [i32], 32, (sequence "DR%u", 0, 7)>; 327 328// Control registers. 329def CONTROL_REG : RegisterClass<"X86", [i64], 64, (sequence "CR%u", 0, 15)>; 330 331// GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of 332// GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d" 333// registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers 334// that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD, 335// and GR64_ABCD are classes for registers that support 8-bit h-register 336// operations. 337def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, (add AL, CL, DL, BL)>; 338def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>; 339def GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)> { 340 let SubRegClasses = [(GR8_ABCD_L sub_8bit), (GR8_ABCD_H sub_8bit_hi)]; 341} 342def GR32_ABCD : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, EBX)> { 343 let SubRegClasses = [(GR8_ABCD_L sub_8bit), 344 (GR8_ABCD_H sub_8bit_hi), 345 (GR16_ABCD sub_16bit)]; 346} 347def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)> { 348 let SubRegClasses = [(GR8_ABCD_L sub_8bit), 349 (GR8_ABCD_H sub_8bit_hi), 350 (GR16_ABCD sub_16bit), 351 (GR32_ABCD sub_32bit)]; 352} 353def GR32_TC : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX)> { 354 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)]; 355} 356def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI, 357 R8, R9, R11, RIP)> { 358 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), 359 (GR16 sub_16bit), 360 (GR32_TC sub_32bit)]; 361} 362 363def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, 364 R8, R9, R11)>; 365 366// GR8_NOREX - GR8 registers which do not require a REX prefix. 367def GR8_NOREX : RegisterClass<"X86", [i8], 8, 368 (add AL, CL, DL, AH, CH, DH, BL, BH)> { 369 let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)]; 370 let AltOrderSelect = [{ 371 return MF.getTarget().getSubtarget<X86Subtarget>().is64Bit(); 372 }]; 373} 374// GR16_NOREX - GR16 registers which do not require a REX prefix. 375def GR16_NOREX : RegisterClass<"X86", [i16], 16, 376 (add AX, CX, DX, SI, DI, BX, BP, SP)> { 377 let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi)]; 378} 379// GR32_NOREX - GR32 registers which do not require a REX prefix. 380def GR32_NOREX : RegisterClass<"X86", [i32], 32, 381 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP)> { 382 let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi), 383 (GR16_NOREX sub_16bit)]; 384} 385// GR64_NOREX - GR64 registers which do not require a REX prefix. 386def GR64_NOREX : RegisterClass<"X86", [i64], 64, 387 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)> { 388 let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi), 389 (GR16_NOREX sub_16bit), 390 (GR32_NOREX sub_32bit)]; 391} 392 393// GR32_NOAX - GR32 registers except EAX. Used by AddRegFrm of XCHG32 in 64-bit 394// mode to prevent encoding using the 0x90 NOP encoding. xchg %eax, %eax needs 395// to clear upper 32-bits of RAX so is not a NOP. 396def GR32_NOAX : RegisterClass<"X86", [i32], 32, (sub GR32, EAX)> { 397 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)]; 398} 399 400// GR32_NOSP - GR32 registers except ESP. 401def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)> { 402 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)]; 403} 404 405// GR64_NOSP - GR64 registers except RSP (and RIP). 406def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)> { 407 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), 408 (GR16 sub_16bit), 409 (GR32_NOSP sub_32bit)]; 410} 411 412// GR32_NOREX_NOSP - GR32 registers which do not require a REX prefix except 413// ESP. 414def GR32_NOREX_NOSP : RegisterClass<"X86", [i32], 32, 415 (and GR32_NOREX, GR32_NOSP)> { 416 let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi), 417 (GR16_NOREX sub_16bit)]; 418} 419 420// GR64_NOREX_NOSP - GR64_NOREX registers except RSP. 421def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64, 422 (and GR64_NOREX, GR64_NOSP)> { 423 let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi), 424 (GR16_NOREX sub_16bit), 425 (GR32_NOREX_NOSP sub_32bit)]; 426} 427 428// A class to support the 'A' assembler constraint: EAX then EDX. 429def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)> { 430 let SubRegClasses = [(GR8_ABCD_L sub_8bit), 431 (GR8_ABCD_H sub_8bit_hi), 432 (GR16_ABCD sub_16bit)]; 433} 434 435// Scalar SSE2 floating point registers. 436def FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>; 437 438def FR64 : RegisterClass<"X86", [f64], 64, (add FR32)>; 439 440 441// FIXME: This sets up the floating point register files as though they are f64 442// values, though they really are f80 values. This will cause us to spill 443// values as 64-bit quantities instead of 80-bit quantities, which is much much 444// faster on common hardware. In reality, this should be controlled by a 445// command line option or something. 446 447def RFP32 : RegisterClass<"X86",[f32], 32, (sequence "FP%u", 0, 6)>; 448def RFP64 : RegisterClass<"X86",[f64], 32, (add RFP32)>; 449def RFP80 : RegisterClass<"X86",[f80], 32, (add RFP32)>; 450 451// Floating point stack registers (these are not allocatable by the 452// register allocator - the floating point stackifier is responsible 453// for transforming FPn allocations to STn registers) 454def RST : RegisterClass<"X86", [f80, f64, f32], 32, (sequence "ST%u", 0, 7)> { 455 let isAllocatable = 0; 456} 457 458// Generic vector registers: VR64 and VR128. 459def VR64: RegisterClass<"X86", [x86mmx], 64, (sequence "MM%u", 0, 7)>; 460def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 461 128, (add FR32)> { 462 let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd)]; 463} 464 465def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 466 256, (sequence "YMM%u", 0, 15)> { 467 let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd), (VR128 sub_xmm)]; 468} 469 470// Status flags registers. 471def CCR : RegisterClass<"X86", [i32], 32, (add EFLAGS)> { 472 let CopyCost = -1; // Don't allow copying of status registers. 473 let isAllocatable = 0; 474} 475