| /external/llvm/test/CodeGen/PowerPC/ |
| D | no-rlwimi-trivial-commute.mir | 86 STW %4, 0, %1 :: (store 4 into %ir.0)
88 STW %8, 0, %1 :: (store 4 into %ir.0)
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| D | addisdtprelha-nonr3.mir | 74 STW killed %r6, 0, killed %x3 :: (store 4 into @y)
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| D | aantidep-def-ec.mir | 104 STW killed %r3, 0, killed %x30 :: (volatile store 4 into %ir.p2)
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 82 case PPC::STW: in isStoreToStackSlot()
339 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) in StoreRegToStackSlot()
348 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) in StoreRegToStackSlot()
412 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) in StoreRegToStackSlot()
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| D | PPCHazardRecognizers.cpp | 261 case PPC::STW: case PPC::STW8: in EmitInstruction()
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| D | PPCRegisterInfo.cpp | 81 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; in PPCRegisterInfo()
485 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) in lowerCRSpilling()
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| D | PPCFrameLowering.cpp | 331 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) in emitPrologue()
337 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) in emitPrologue()
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| D | PPCInstrInfo.td | 754 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
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| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaLLRP.cpp | 68 case Alpha::STW: case Alpha::STB: in runOnMachineFunction()
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| D | AlphaInstrInfo.cpp | 59 case Alpha::STW: in isStoreToStackSlot()
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| D | AlphaInstrInfo.td | 453 def STW : MForm<0x0D, 0, "stw $RA,$DISP($RB)",
567 (STW GPRC:$DATA, 0, GPRC:$addr)>;
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 70 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; in PPCRegisterInfo()
526 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) in lowerCRSpilling()
613 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) in lowerCRBitSpilling()
690 BuildMI(MBB, II, dl, TII.get(PPC::STW)).addReg(Reg, RegState::Kill), in lowerVRSAVESpilling()
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| D | PPCFrameLowering.cpp | 757 : PPC::STW ); in emitPrologue()
1764 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW)) in spillCalleeSavedRegisters()
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| D | PPCInstrInfo.cpp | 298 case PPC::STW: in isStoreToStackSlot()
968 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) in StoreRegToStackSlot()
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| D | PPCFastISel.cpp | 639 Opc = PPC::STW; in PPCEmitStore()
706 case PPC::STW : Opc = PPC::STWX; break; in PPCEmitStore()
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| D | PPCISelDAGToDAG.cpp | 4298 case PPC::STW: in PeepholePPC64()
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| D | PPCInstrInfo.td | 1791 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
4213 def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW gprc:$val, memri:$ptr)>;
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| D | PPCISelLowering.cpp | 8727 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW)) in emitEHSjLjSetJmp()
8760 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW)) in emitEHSjLjSetJmp()
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| /external/v8/src/ppc/ |
| D | disasm-ppc.cc | 1313 case STW: { in InstructionDecode()
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| D | constants-ppc.h | 1741 V(stw, STW, 0x90000000) \
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| D | assembler-ppc.cc | 1324 d_form(STW, dst, src.ra(), src.offset(), true); in stw()
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| D | simulator-ppc.cc | 3721 case STW: { in ExecuteGeneric()
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| /external/llvm/lib/Target/AVR/ |
| D | AVRInstrInfo.td | 1238 // STW P, Rr+1:Rr
1266 // STW P+, Rr+1:Rr
1292 // STW -P, Rr+1:Rr
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| /external/llvm/lib/Target/BPF/ |
| D | BPFInstrInfo.td | 319 def STW : STOREi64<0x0, "stw", truncstorei32>;
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativePPC_common.c | 215 #define STW (HI(36)) macro
571 #define STACK_STORE STW
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