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Searched refs:SWR (Results 1 – 19 of 19) sorted by relevance

/external/mesa3d/src/gallium/docs/source/drivers/openswr/
Dfaq.rst26 SWR is a tile based immediate mode renderer with a sort-free threading
38 shader and fragment shaders, streamout, and fragment blending. SWR
72 of writing. Core SWR undergoes rigorous unit testing and we are quite
77 and SWR. Fixing these issues is one of our major future development
100 * Features - core SWR has a lot of functionality we have yet to
132 * You don't need a fire-breathing Xeon machine to work on SWR - we do
Dusage.rst37 SWR detected AVX2
/external/tcpdump/tests/
Dpimv2_sm-v.out20 joined source #1: 1.1.1.1(SWR)
54 joined source #1: 1.1.1.1(SWR)
90 joined source #1: 1.1.1.1(SWR)
124 joined source #1: 1.1.1.1(SWR)
160 joined source #1: 1.1.1.1(SWR)
196 joined source #1: 1.1.1.1(SWR)
230 joined source #1: 1.1.1.1(SWR)
266 joined source #1: 1.1.1.1(SWR)
286 pruned source #1: 1.1.1.1(SWR)
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsNaClELFStreamer.cpp233 case Mips::SWR: in isBasePlusOffsetMemoryAccess()
/external/mesa3d/src/gallium/drivers/swr/
DSConscript202 # main SWR lib
/external/v8/src/mips/
Dconstants-mips.h383 SWR = ((5U << 3) + 6) << kOpcodeShift, enumerator
917 OpcodeToBitNumber(SWL) | OpcodeToBitNumber(SW) | OpcodeToBitNumber(SWR) |
Ddisasm-mips.cc1642 case SWR: in DecodeTypeImmediate()
Dassembler-mips.cc1945 GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_); in swr()
Dsimulator-mips.cc4507 case SWR: { in DecodeTypeImmediate()
/external/v8/src/mips64/
Dconstants-mips64.h362 SWR = ((5U << 3) + 6) << kOpcodeShift, enumerator
952 OpcodeToBitNumber(SWR) | OpcodeToBitNumber(SDR) |
Ddisasm-mips64.cc1859 case SWR: in DecodeTypeImmediate()
Dassembler-mips64.cc2114 GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_); in swr()
Dsimulator-mips64.cc4754 case SWR: { in DecodeTypeImmediate()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.h205 SWR, enumerator
DMipsInstrInfo.td138 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
1773 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
DMipsISelLowering.cpp150 case MipsISD::SWR: return "MipsISD::SWR"; in getTargetNodeName()
2358 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); in lowerUnalignedIntStore()
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/
DMBlazeDisassembler.cpp400 case 0x1: return MBlaze::SWR; in decodeSW()
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeInstrInfo.td472 def SWR : StoreM<0x36, 0x200, "swr ">;
/external/v8/src/s390/
Dconstants-s390.h1573 V(swr, SWR, 0x2F) /* type = RR SUBTRACT UNNORMALIZED (long HFP) */ \