Searched refs:SchedWrite (Results 1 – 12 of 12) sorted by relevance
/external/llvm/lib/Target/AArch64/ |
D | AArch64Schedule.td | 21 def WriteImm : SchedWrite; // MOVN, MOVZ 25 def WriteI : SchedWrite; // ALU 26 def WriteISReg : SchedWrite; // ALU of Shifted-Reg 27 def WriteIEReg : SchedWrite; // ALU of Extended-Reg 31 def WriteExtr : SchedWrite; // EXTR shifts a reg pair 33 def WriteIS : SchedWrite; // Shift/Scale 34 def WriteID32 : SchedWrite; // 32-bit Divide 35 def WriteID64 : SchedWrite; // 64-bit Divide 37 def WriteIM32 : SchedWrite; // 32-bit Multiply 38 def WriteIM64 : SchedWrite; // 64-bit Multiply [all …]
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D | AArch64SchedA53.td | 48 // Subtarget-specific SchedWrite types which both map the ProcResources and
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/external/llvm/lib/Target/AMDGPU/ |
D | SISchedule.td | 20 def WriteBranch : SchedWrite; 21 def WriteExport : SchedWrite; 22 def WriteLDS : SchedWrite; 23 def WriteSALU : SchedWrite; 24 def WriteSMEM : SchedWrite; 25 def WriteVMEM : SchedWrite; 26 def WriteBarrier : SchedWrite; 29 def Write32Bit : SchedWrite; 30 def WriteQuarterRate32 : SchedWrite; 31 def WriteFullOrQuarterRate32 : SchedWrite; [all …]
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/external/llvm/lib/Target/ARM/ |
D | ARMSchedule.td | 32 // def WriteALUsr : SchedWrite; 58 def WriteALU : SchedWrite; 62 def WriteALUsi : SchedWrite; // Shift by immediate. 63 def WriteALUsr : SchedWrite; // Shift by register. 64 def WriteALUSsr : SchedWrite; // Shift by register (flag setting). 68 def WriteCMP : SchedWrite; 69 def WriteCMPsi : SchedWrite; 70 def WriteCMPsr : SchedWrite; 73 def WriteDiv : SchedWrite; 76 def WriteLd : SchedWrite; [all …]
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D | ARMScheduleA9.td | 2063 [A9WriteLMLo, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>; 2065 [A9WriteLMHi, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>; 2128 [A9WriteIssue, !cast<SchedWrite>("A9WriteLfp"#NumAddr#Seq)]>; 2133 [A9WriteF, !cast<SchedWrite>("A9WriteLfp"#NumAddr#Seq)]>; 2163 [A9WriteLMfpLo, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>; 2168 [A9WriteLMHi, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
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/external/llvm/lib/Target/Lanai/ |
D | LanaiSchedule.td | 58 def WriteLD : SchedWrite; 59 def WriteST : SchedWrite; 60 def WriteLDSW : SchedWrite; 61 def WriteSTSW : SchedWrite; 62 def WriteALU : SchedWrite;
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/external/llvm/include/llvm/Target/ |
D | TargetSchedule.td | 209 // instruction. One SchedWrite type must be listed for each explicit 210 // def operand in order. Additional SchedWrite types may optionally be 217 // single SchedWrite and single SchedRead in any order. 223 class SchedWrite : SchedReadWrite; 224 def NoWrite : SchedWrite; 229 // Define a SchedWrite that is modeled as a sequence of other 239 class WriteSequence<list<SchedWrite> writes, int rep = 1> : SchedWrite { 240 list<SchedWrite> Writes = writes; 261 // Define the resources and latency of a SchedWrite. This will be used 263 // SchedWrite is defined by the target, while WriteResources is [all …]
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/external/llvm/lib/Target/X86/ |
D | X86Schedule.td | 21 def WriteRMW : SchedWrite; 23 // Most instructions can fold loads, so almost every SchedWrite comes in two 25 // An X86FoldableSchedWrite holds a reference to the corresponding SchedWrite 27 class X86FoldableSchedWrite : SchedWrite { 28 // The SchedWrite to use when a load is folded into the instruction. 29 SchedWrite Folded; 35 def Ld : SchedWrite; 38 let Folded = !cast<SchedWrite>(NAME#"Ld"); 45 def WriteIMulH : SchedWrite; // Integer multiplication, high part. 47 def WriteLEA : SchedWrite; // LEA instructions can't fold loads. [all …]
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D | X86InstrArithmetic.td | 49 class SchedLoadReg<SchedWrite SW> : Sched<[SW,
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D | X86InstrSSE.td | 7785 PatFrag ld_frag, SchedWrite Sched> : 7793 ValueType ResVT, ValueType OpVT, SchedWrite Sched> :
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/external/llvm/utils/TableGen/ |
D | SubtargetEmitter.cpp | 93 Record *FindWriteResources(const CodeGenSchedRW &SchedWrite, 649 const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) { in FindWriteResources() argument 653 if (SchedWrite.TheDef->isSubClassOf("SchedWriteRes")) in FindWriteResources() 654 return SchedWrite.TheDef; in FindWriteResources() 657 for (Record *A : SchedWrite.Aliases) { in FindWriteResources() 680 || SchedWrite.TheDef == WR->getValueAsDef("WriteType")) { in FindWriteResources() 694 + SchedWrite.TheDef->getName()); in FindWriteResources()
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D | CodeGenSchedule.cpp | 424 const CodeGenSchedRW &SchedWrite = getSchedRW(RWIdx, IsRead); in expandRWSeqForProc() local 426 for (RecIter AI = SchedWrite.Aliases.begin(), AE = SchedWrite.Aliases.end(); in expandRWSeqForProc() 445 if (!SchedWrite.IsSequence) { in expandRWSeqForProc() 450 SchedWrite.TheDef ? SchedWrite.TheDef->getValueAsInt("Repeat") : 1; in expandRWSeqForProc() 452 for (IdxIter I = SchedWrite.Sequence.begin(), E = SchedWrite.Sequence.end(); in expandRWSeqForProc()
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