1//=-LanaiSchedule.td - Lanai Scheduling Definitions --*- tablegen -*-=========// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10def ALU_FU : FuncUnit; 11def LDST_FU : FuncUnit; 12 13def IIC_ALU : InstrItinClass; 14def IIC_LD : InstrItinClass; 15def IIC_ST : InstrItinClass; 16def IIC_LDSW : InstrItinClass; 17def IIC_STSW : InstrItinClass; 18 19def LanaiItinerary : ProcessorItineraries<[ALU_FU, LDST_FU],[],[ 20 InstrItinData<IIC_LD, [InstrStage<1, [LDST_FU]>]>, 21 InstrItinData<IIC_ST, [InstrStage<1, [LDST_FU]>]>, 22 InstrItinData<IIC_LDSW, [InstrStage<2, [LDST_FU]>]>, 23 InstrItinData<IIC_STSW, [InstrStage<2, [LDST_FU]>]>, 24 InstrItinData<IIC_ALU, [InstrStage<1, [ALU_FU]>]> 25]>; 26 27def LanaiSchedModel : SchedMachineModel { 28 // Cycles for loads to access the cache [default = -1] 29 let LoadLatency = 2; 30 31 // Max micro-ops that can be buffered for optimized loop dispatch/execution. 32 // [default = -1] 33 let LoopMicroOpBufferSize = 0; 34 35 // Allow scheduler to assign default model to any unrecognized opcodes. 36 // [default = 1] 37 let CompleteModel = 0; 38 39 // Max micro-ops that may be scheduled per cycle. [default = 1] 40 let IssueWidth = 1; 41 42 // Extra cycles for a mispredicted branch. [default = -1] 43 let MispredictPenalty = 10; 44 45 // Enable Post RegAlloc Scheduler pass. [default = 0] 46 let PostRAScheduler = 0; 47 48 // Max micro-ops that can be buffered. [default = -1] 49 let MicroOpBufferSize = 0; 50 51 // Per-cycle resources tables. [default = NoItineraries] 52 let Itineraries = LanaiItinerary; 53} 54 55def ALU : ProcResource<1> { let BufferSize = 0; } 56def LdSt : ProcResource<1> { let BufferSize = 0; } 57 58def WriteLD : SchedWrite; 59def WriteST : SchedWrite; 60def WriteLDSW : SchedWrite; 61def WriteSTSW : SchedWrite; 62def WriteALU : SchedWrite; 63 64let SchedModel = LanaiSchedModel in { 65 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; } 66 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; } 67 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; } 68 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; } 69 def : WriteRes<WriteALU, [ALU]> { let Latency = 1; } 70} 71