Searched refs:SrcReg1 (Results 1 – 4 of 4) sorted by relevance
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 872 unsigned SrcReg1 = getRegForValue(SrcValue1); in PPCEmitCmp() local
873 if (SrcReg1 == 0) in PPCEmitCmp()
885 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
887 SrcReg1 = ExtReg; in PPCEmitCmp()
899 .addReg(SrcReg1).addReg(SrcReg2); in PPCEmitCmp()
902 .addReg(SrcReg1).addImm(Imm); in PPCEmitCmp()
1204 unsigned SrcReg1 = getRegForValue(I->getOperand(0)); in SelectBinaryIntOp() local
1205 if (SrcReg1 == 0) return false; in SelectBinaryIntOp()
1218 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1222 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1422 unsigned SrcReg1 = getRegForValue(Src1Value); in ARMEmitCmp() local
1423 if (SrcReg1 == 0) return false; in ARMEmitCmp()
1433 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt); in ARMEmitCmp()
1434 if (SrcReg1 == 0) return false; in ARMEmitCmp()
1442 SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0); in ARMEmitCmp()
1446 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1450 .addReg(SrcReg1); in ARMEmitCmp()
1758 unsigned SrcReg1 = getRegForValue(I->getOperand(0)); in SelectBinaryIntOp() local
1759 if (SrcReg1 == 0) return false; in SelectBinaryIntOp()
1767 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1); in SelectBinaryIntOp()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 3292 unsigned SrcReg1 = MUL->getOperand(2).getReg(); in genFusedMultiply() local
3301 if (TargetRegisterInfo::isVirtualRegister(SrcReg1)) in genFusedMultiply()
3302 MRI.constrainRegClass(SrcReg1, RC); in genFusedMultiply()
3310 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genFusedMultiply()
3316 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genFusedMultiply()
3322 .addReg(SrcReg1, getKillRegState(Src1IsKill)); in genFusedMultiply()
3356 unsigned SrcReg1 = MUL->getOperand(2).getReg(); in genMaddR() local
3363 if (TargetRegisterInfo::isVirtualRegister(SrcReg1)) in genMaddR()
3364 MRI.constrainRegClass(SrcReg1, RC); in genMaddR()
3371 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genMaddR()
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| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_program_alu.c | 63 struct rc_src_register SrcReg0, struct rc_src_register SrcReg1) in emit2() argument
74 fpi->U.I.SrcReg[1] = SrcReg1; in emit2()
82 struct rc_src_register SrcReg0, struct rc_src_register SrcReg1, in emit3() argument
94 fpi->U.I.SrcReg[1] = SrcReg1; in emit3()
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