| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AdvSIMDScalarPass.cpp | 215 unsigned SubReg1; in isProfitableToTransform() local
233 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1); in isProfitableToTransform()
307 unsigned Src1 = 0, SubReg1; in transformInstruction() local
332 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1); in transformInstruction()
356 SubReg1 = 0; in transformInstruction()
372 .addReg(Src1, getKillRegState(KillSrc1), SubReg1); in transformInstruction()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1457 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32); in PairSRegs() local
1458 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in PairSRegs()
1468 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32); in PairDRegs() local
1469 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in PairDRegs()
1479 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32); in PairQRegs() local
1480 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in PairQRegs()
1492 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32); in QuadSRegs() local
1495 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in QuadSRegs()
1507 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32); in QuadDRegs() local
1510 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in QuadDRegs()
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1601 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32); in createGPRPairNode() local
1602 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createGPRPairNode()
1612 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); in createSRegPairNode() local
1613 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createSRegPairNode()
1623 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32); in createDRegPairNode() local
1624 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createDRegPairNode()
1634 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32); in createQRegPairNode() local
1635 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createQRegPairNode()
1646 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); in createQuadSRegsNode() local
1649 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadSRegsNode()
[all …]
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| D | ARMISelLowering.cpp | 7109 SDValue SubReg1 = DAG.getTargetConstant(ARM::gsub_1, dl, MVT::i32); in createGPRPairNode() local
7110 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 }; in createGPRPairNode()
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| /external/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 147 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg(); in commuteInstructionImpl() local
166 SubReg0 = SubReg1; in commuteInstructionImpl()
184 CommutedMI->getOperand(Idx2).setSubReg(SubReg1); in commuteInstructionImpl()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 364 SDValue RC, SubReg0, SubReg1; in Select() local
372 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32); in Select()
376 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in Select()
381 N->getOperand(1), SubReg1 }; in Select()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 351 unsigned SubReg1 = MI.getOperand(1).getSubReg(); in commuteInstructionImpl() local
362 assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch"); in commuteInstructionImpl()
394 MI.getOperand(2).setSubReg(SubReg1); in commuteInstructionImpl()
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