| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 620 const TargetRegisterClass *SuperRC = in FindSuitableFreeRegisters() local
623 ArrayRef<unsigned> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
631 if (RenameOrder.count(SuperRC) == 0) in FindSuitableFreeRegisters()
632 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size())); in FindSuitableFreeRegisters()
634 unsigned OrigR = RenameOrder[SuperRC]; in FindSuitableFreeRegisters()
701 RenameOrder.erase(SuperRC); in FindSuitableFreeRegisters()
702 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R)); in FindSuitableFreeRegisters()
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| D | MachineVerifier.cpp | 770 const TargetRegisterClass *SuperRC = in visitMachineOperand() local
772 if (!SuperRC) { in visitMachineOperand()
776 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
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| /external/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 611 const TargetRegisterClass *SuperRC = in FindSuitableFreeRegisters() local
614 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
622 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size())); in FindSuitableFreeRegisters()
624 unsigned OrigR = RenameOrder[SuperRC]; in FindSuitableFreeRegisters()
717 RenameOrder.erase(SuperRC); in FindSuitableFreeRegisters()
718 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R)); in FindSuitableFreeRegisters()
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| D | RegAllocGreedy.cpp | 1560 const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC, in getNumAllocatableRegsForConstraints() argument
1563 assert(SuperRC && "Invalid register class"); in getNumAllocatableRegsForConstraints()
1566 MI->getRegClassConstraintEffectForVReg(Reg, SuperRC, TII, TRI, in getNumAllocatableRegsForConstraints()
1599 const TargetRegisterClass *SuperRC = in tryInstructionSplit() local
1601 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC); in tryInstructionSplit()
1610 getNumAllocatableRegsForConstraints(MI, VirtReg.reg, SuperRC, TII, in tryInstructionSplit()
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| D | TargetLoweringBase.cpp | 1277 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); in findRepresentativeClass() local
1279 if (SuperRC->getSize() <= BestRC->getSize()) in findRepresentativeClass()
1281 if (!isLegalRC(SuperRC)) in findRepresentativeClass()
1283 BestRC = SuperRC; in findRepresentativeClass()
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| D | MachineVerifier.cpp | 1031 const TargetRegisterClass *SuperRC = in visitMachineOperand() local
1033 if (!SuperRC) { in visitMachineOperand()
1037 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SILoadStoreOptimizer.cpp | 229 const TargetRegisterClass *SuperRC in mergeRead2Pair() local
231 unsigned DestReg = MRI->createVirtualRegister(SuperRC); in mergeRead2Pair()
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| D | SIInstrInfo.h | 47 const TargetRegisterClass *SuperRC,
53 const TargetRegisterClass *SuperRC,
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| D | SILowerControlFlow.cpp | 604 const TargetRegisterClass *SuperRC = TRI->getPhysRegClass(VecReg); in computeIndirectRegAndOffset() local
606 int NumElts = SuperRC->getSize() / RC->getSize(); in computeIndirectRegAndOffset()
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| D | SIInstrInfo.cpp | 1904 const TargetRegisterClass *SuperRC, in buildExtractSubReg() argument
1922 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC); in buildExtractSubReg()
1937 const TargetRegisterClass *SuperRC, in buildExtractSubRegOrImm() argument
1950 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC, in buildExtractSubRegOrImm()
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| D | AMDGPUISelDAGToDAG.cpp | 208 const TargetRegisterClass *SuperRC = in getOperandRegClass() local
213 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC, in getOperandRegClass()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.h | 365 CodeGenRegisterClass *SuperRC) { in addSuperRegClass() argument
366 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()
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