| /external/mesa3d/src/gallium/drivers/r300/compiler/tests/ |
| D | regalloc_tex_1d_swizzle.test | 2 0: TEX temp[8].xyz, input[1].xy__, 2D[0];
3 1: TEX temp[10].xyz, input[2].xyz_, CUBE[2];
4 2: TEX temp[12].xyz, input[1].xy__, 2D[1];
11 9: TEX temp[18].x, temp[0].x___, 1D[3];
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | vtx-fetch-branch.ll | 11 ; CHECK: TEX
|
| D | tex-clause-antidep.ll | 3 ;CHECK: TEX
|
| D | rv7x0_count3.ll | 3 ; CHECK: TEX 9 @6 ; encoding: [0x06,0x00,0x00,0x00,0x00,0x04,0x88,0x80]
|
| /external/mesa3d/src/gallium/state_trackers/nine/ |
| D | nine_shader.c | 2815 DECL_SPECIAL(TEX) in DECL_SPECIAL() argument
2958 _OPI(TEX, TEX, V(0,0), V(0,0), V(0,0), V(1,3), 1, 0, SPECIAL(TEX)),
2959 _OPI(TEX, TEX, V(0,0), V(0,0), V(1,4), V(1,4), 1, 1, SPECIAL(TEXLD_14)),
2960 _OPI(TEX, TEX, V(0,0), V(0,0), V(2,0), V(3,0), 1, 2, SPECIAL(TEXLD)),
2961 _OPI(TEXBEM, TEX, V(0,0), V(0,0), V(0,0), V(1,3), 1, 1, SPECIAL(TEXBEM)),
2962 _OPI(TEXBEML, TEX, V(0,0), V(0,0), V(0,0), V(1,3), 1, 1, SPECIAL(TEXBEM)),
2963 _OPI(TEXREG2AR, TEX, V(0,0), V(0,0), V(0,0), V(1,3), 1, 1, SPECIAL(TEXREG2AR)),
2964 _OPI(TEXREG2GB, TEX, V(0,0), V(0,0), V(0,0), V(1,3), 1, 1, SPECIAL(TEXREG2GB)),
2965 _OPI(TEXM3x2PAD, TEX, V(0,0), V(0,0), V(0,0), V(1,3), 1, 1, SPECIAL(TEXM3x2PAD)),
2966 _OPI(TEXM3x2TEX, TEX, V(0,0), V(0,0), V(0,0), V(1,3), 1, 1, SPECIAL(TEXM3x2TEX)),
[all …]
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | R600Defines.h | 33 TEX = (1 << 1), enumerator
|
| D | EvergreenInstructions.td | 649 "TEX $COUNT @$ADDR"> {
|
| D | R600Instructions.td | 1218 "TEX $CNT @$ADDR"> {
|
| /external/swiftshader/src/Shader/ |
| D | VertexProgram.hpp | 111 void TEX(Vector4f &dst, Vector4f &src, const Src&);
|
| D | PixelPipeline.hpp | 88 void TEX(Vector4s &dst, Float4 &u, Float4 &v, Float4 &s, int stage, bool project);
|
| D | PixelPipeline.cpp | 166 TEX(d, x, y, z, dst.index, false); in applyShader()
174 …TEX(d, x, y, z, dst.index, src0.modifier == Shader::MODIFIER_DZ || src0.modifier == Shader::MODIFI… in applyShader()
178 …TEX(d, x, y, w, dst.index, src0.modifier == Shader::MODIFIER_DZ || src0.modifier == Shader::MODIFI… in applyShader()
1676 void PixelPipeline::TEX(Vector4s &dst, Float4 &u, Float4 &v, Float4 &s, int sampler, bool project) in TEX() function in sw::PixelPipeline
|
| D | VertexProgram.cpp | 339 case Shader::OPCODE_TEX: TEX(d, s0, src1); break; in program()
1573 void VertexProgram::TEX(Vector4f &dst, Vector4f &src0, const Src &src1) in TEX() function in sw::VertexProgram
|
| /external/mesa3d/src/mesa/program/ |
| D | program_lexer.l | 226 TEX{sat} { return_opcode(require_ARB_fp, SAMPLE_OP, TEX, 3); }
|
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_opcode_tmp.h | 103 OP12_TEX(TEX)
|
| /external/mesa3d/src/gallium/docs/source/cso/ |
| D | sampler.rst | 94 the texture coordinates and/or the fragment shader TEX/TXB/TXL
|
| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_from_tgsi.cpp | 746 NV50_IR_OPCODE_CASE(TEX, TEX); in translateOpcode()
748 NV50_IR_OPCODE_CASE(TXP, TEX); in translateOpcode()
838 NV50_IR_OPCODE_CASE(SAMPLE, TEX); in translateOpcode()
840 NV50_IR_OPCODE_CASE(SAMPLE_C, TEX); in translateOpcode()
841 NV50_IR_OPCODE_CASE(SAMPLE_C_LZ, TEX); in translateOpcode()
860 NV50_IR_OPCODE_CASE(TEX2, TEX); in translateOpcode()
|
| /external/mesa3d/src/gallium/drivers/nouveau/nv30/ |
| D | nvfx_fragprog.c | 754 nvfx_fp_emit(fpc, tex(sat, TEX, unit, dst, mask, src[0], none, none)); in nvfx_fragprog_parse_instruction()
776 nvfx_fp_emit(fpc, tex(sat, TEX, unit, dst, mask, src[0], none, none)); in nvfx_fragprog_parse_instruction()
|
| /external/mesa3d/docs/relnotes/ |
| D | 5.1 | 45 - the TEX and TXP instructions both do perspective correction
|
| /external/mesa3d/src/gallium/drivers/r600/sb/ |
| D | sb_bc_fmt_def.inc | 479 // TEX
|
| D | notes.markdown | 322 vector operand in the CF/TEX/VTX instructions is represented with 4
|
| /external/mesa3d/src/gallium/docs/source/ |
| D | tgsi.rst | 544 .. opcode:: TEX - Texture Lookup
572 this is the same as TEX, but uses another reg to encode the
1004 used. Set W to zero. It behaves like the TEX instruction, but a filtered
3376 For TEX\* style texture sample opcodes (as opposed to SAMPLE\* opcodes
3386 NOTE: It is NOT legal to mix SAMPLE\* style opcodes and TEX\* opcodes
3561 by TGSI texture instructions, such as :opcode:`TEX`, :opcode:`TXD`, and
|
| D | screen.rst | 38 can do the depth texture / Z comparison operation in TEX instructions
|
| /external/mesa3d/docs/ |
| D | VERSIONS | 1261 - frag prog TEX instruction no longer incorrectly divides s,t,r by q
1262 - ARB frag prog TEX and TEXP instructions now use LOD=0
|
| /external/mesa3d/src/gallium/drivers/etnaviv/ |
| D | etnaviv_compiler.c | 1792 INSTR(TEX, trans_sampler),
|
| /external/icu/android_icu4j/src/main/tests/android/icu/dev/data/unicode/ |
| D | UnicodeData.txt | 12321 A12D;YI SYLLABLE TEX;Lo;0;L;;;;;N;;;;;
|