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Searched refs:TIED_TO (Results 1 – 25 of 28) sorted by relevance

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/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h633 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0) in getOperandBias()
635 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && in getOperandBias()
636 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1) in getOperandBias()
640 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && in getOperandBias()
641 Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1) in getOperandBias()
645 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps - 2, MCOI::TIED_TO) == 0) in getOperandBias()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMCodeEmitter.cpp1062 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in emitDataProcessingInstruction()
1142 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in emitLoadStoreInstruction()
1213 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in emitMiscLoadStoreInstruction()
1604 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in emitVFPArithInstruction()
1876 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in emitNEON2RegInstruction()
1891 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in emitNEON3RegInstruction()
1894 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in emitNEON3RegInstruction()
/external/swiftshader/third_party/LLVM/include/llvm/MC/
DMCInstrDesc.h29 TIED_TO = 0, // Must be allocated the same register as. enumerator
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DTargetInstrInfoImpl.cpp85 MI->getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) { in commuteInstruction()
89 MI->getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) { in commuteInstruction()
DMachineInstr.cpp1029 MCID.getOperandConstraint(i, MCOI::TIED_TO) == (int)DefOpIdx) { in isRegTiedToUseOperand()
1081 int DefIdx = MCID.getOperandConstraint(UseOpIdx, MCOI::TIED_TO); in isRegTiedToDefOperand()
DRegAllocFast.cpp887 MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1; in AllocateBasicBlock()
/external/llvm/include/llvm/MC/
DMCInstrDesc.h34 TIED_TO = 0, // Must be allocated the same register as. enumerator
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86CodeEmitter.cpp162 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1; in determineREX()
719 if (NumOps > 1 && Desc->getOperandConstraint(1, MCOI::TIED_TO) != -1) in emitInstruction()
721 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1,MCOI::TIED_TO)== 0) in emitInstruction()
DX86GenInstrInfo.inc3923 …{ { -1, 0, 0, MCOI::OPERAND_UNKNOWN }, { -1, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_…
3936 …::OPERAND_REGISTER }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_…
3937 …::OPERAND_REGISTER }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_…
3938 …::OPERAND_REGISTER }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_…
3940 …::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_…
3941 …::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_…
3942 …::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_…
3944 …::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_…
3945 …::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_…
3946 …::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_…
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp634 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1; in DetermineREXPrefix()
852 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1) in EncodeInstruction()
854 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, MCOI::TIED_TO)== 0) in EncodeInstruction()
/external/llvm/lib/Target/SystemZ/
DSystemZShortenInst.cpp68 if (MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && in tieOpsIfNeeded()
/external/llvm/lib/CodeGen/
DTargetInstrInfo.cpp158 MI.getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) { in commuteInstructionImpl()
163 MI.getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) { in commuteInstructionImpl()
DMachineVerifier.cpp916 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO); in visitMachineOperand()
952 if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO)) in visitMachineOperand()
DMIRPrinter.cpp532 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO); in hasComplexRegisterTies()
DRegAllocFast.cpp944 MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1; in AllocateBasicBlock()
DMachineInstr.cpp849 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); in addOperand()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DScheduleDAGFast.cpp254 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in CopyAndMoveSuccessors()
DScheduleDAGSDNodes.cpp396 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in AddSchedEdges()
DScheduleDAGRRList.cpp842 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in CopyAndMoveSuccessors()
2613 if (MCID.getOperandConstraint(i+NumRes, MCOI::TIED_TO) != -1) { in canClobber()
2830 if (MCID.getOperandConstraint(j+NumRes, MCOI::TIED_TO) == -1) in AddPseudoTwoAddrDeps()
DInstrEmitter.cpp323 bool isTied = MI->getDesc().getOperandConstraint(Idx, MCOI::TIED_TO) != -1; in AddRegisterOperand()
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGRRList.cpp1013 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in CopyAndMoveSuccessors()
2679 if (MCID.getOperandConstraint(i+NumRes, MCOI::TIED_TO) != -1) { in canClobber()
2901 if (MCID.getOperandConstraint(j+NumRes, MCOI::TIED_TO) == -1) in AddPseudoTwoAddrDeps()
DScheduleDAGFast.cpp259 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in CopyAndMoveSuccessors()
DScheduleDAGSDNodes.cpp434 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in AddSchedEdges()
DInstrEmitter.cpp363 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1; in AddRegisterOperand()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCInstrInfo.cpp127 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) && in commuteInstruction()

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