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Searched refs:TargetOpcode (Results 1 – 25 of 192) sorted by relevance

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/external/llvm/lib/CodeGen/
DPatchableFunction.cpp46 case TargetOpcode::IMPLICIT_DEF: in doesNotGeneratecode()
47 case TargetOpcode::KILL: in doesNotGeneratecode()
48 case TargetOpcode::CFI_INSTRUCTION: in doesNotGeneratecode()
49 case TargetOpcode::EH_LABEL: in doesNotGeneratecode()
50 case TargetOpcode::GC_LABEL: in doesNotGeneratecode()
51 case TargetOpcode::DBG_VALUE: in doesNotGeneratecode()
73 TII->get(TargetOpcode::PATCHABLE_OP)) in runOnMachineFunction()
DDetectDeadLanes.cpp145 case TargetOpcode::COPY: in lowersToCopies()
146 case TargetOpcode::PHI: in lowersToCopies()
147 case TargetOpcode::INSERT_SUBREG: in lowersToCopies()
148 case TargetOpcode::REG_SEQUENCE: in lowersToCopies()
149 case TargetOpcode::EXTRACT_SUBREG: in lowersToCopies()
170 case TargetOpcode::INSERT_SUBREG: in isCrossCopy()
174 case TargetOpcode::REG_SEQUENCE: { in isCrossCopy()
179 case TargetOpcode::EXTRACT_SUBREG: { in isCrossCopy()
240 case TargetOpcode::COPY: in transferUsedLanes()
241 case TargetOpcode::PHI: in transferUsedLanes()
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DExpandPostRAPseudos.cpp103 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
114 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
141 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
156 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
211 case TargetOpcode::SUBREG_TO_REG: in runOnMachineFunction()
214 case TargetOpcode::COPY: in runOnMachineFunction()
217 case TargetOpcode::DBG_VALUE: in runOnMachineFunction()
219 case TargetOpcode::INSERT_SUBREG: in runOnMachineFunction()
220 case TargetOpcode::EXTRACT_SUBREG: in runOnMachineFunction()
DStackColoring.cpp428 assert((MI.getOpcode() == TargetOpcode::LIFETIME_START || in getStartOrEndSlot()
429 MI.getOpcode() == TargetOpcode::LIFETIME_END) && in getStartOrEndSlot()
448 if (MI.getOpcode() == TargetOpcode::LIFETIME_START || in isLifetimeStartOrEnd()
449 MI.getOpcode() == TargetOpcode::LIFETIME_END) { in isLifetimeStartOrEnd()
456 if (MI.getOpcode() == TargetOpcode::LIFETIME_END) { in isLifetimeStartOrEnd()
519 if (MI.getOpcode() == TargetOpcode::LIFETIME_START || in collectMarkers()
520 MI.getOpcode() == TargetOpcode::LIFETIME_END) { in collectMarkers()
525 if (MI.getOpcode() == TargetOpcode::LIFETIME_START) { in collectMarkers()
535 DEBUG(dbgs() << (MI.getOpcode() == TargetOpcode::LIFETIME_START in collectMarkers()
841 if (I.getOpcode() == TargetOpcode::LIFETIME_START || in remapInstructions()
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DXRayInstrumentation.cpp65 TII->get(TargetOpcode::PATCHABLE_FUNCTION_ENTER)); in runOnMachineFunction()
77 TII->get(TargetOpcode::PATCHABLE_RET)) in runOnMachineFunction()
DMachineSSAUpdater.cpp150 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF, in GetValueInMiddleOfBlock()
187 MachineInstrBuilder InsertedPHI = InsertNewDef(TargetOpcode::PHI, BB, in GetValueInMiddleOfBlock()
287 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF, in GetUndefVal()
299 MachineInstr *PHI = InsertNewDef(TargetOpcode::PHI, BB, Loc, in CreateEmptyPHI()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DMachineInstr.h258 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
259 getOpcode() == TargetOpcode::EH_LABEL ||
260 getOpcode() == TargetOpcode::GC_LABEL;
264 return getOpcode() == TargetOpcode::PROLOG_LABEL;
266 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
267 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
268 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
270 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
271 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
272 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
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/external/llvm/include/llvm/CodeGen/
DMachineInstr.h775 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
776 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
781 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
787 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
796 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
797 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
798 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
799 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
801 return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect();
806 return getOpcode() == TargetOpcode::INSERT_SUBREG;
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/external/llvm/lib/Target/Hexagon/
DHexagonMachineScheduler.cpp53 case TargetOpcode::EXTRACT_SUBREG: in isResourceAvailable()
54 case TargetOpcode::INSERT_SUBREG: in isResourceAvailable()
55 case TargetOpcode::SUBREG_TO_REG: in isResourceAvailable()
56 case TargetOpcode::REG_SEQUENCE: in isResourceAvailable()
57 case TargetOpcode::IMPLICIT_DEF: in isResourceAvailable()
58 case TargetOpcode::COPY: in isResourceAvailable()
59 case TargetOpcode::INLINEASM: in isResourceAvailable()
105 case TargetOpcode::EXTRACT_SUBREG: in reserveResources()
106 case TargetOpcode::INSERT_SUBREG: in reserveResources()
107 case TargetOpcode::SUBREG_TO_REG: in reserveResources()
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DHexagonGenPredicate.cpp191 case TargetOpcode::COPY: in collectPredicateGPR()
237 if (Opc == Hexagon::C2_tfrpr || Opc == TargetOpcode::COPY) { in getPredRegFor()
254 BuildMI(B, std::next(DefIt), DL, TII->get(TargetOpcode::COPY), NewPR) in getPredRegFor()
314 case TargetOpcode::COPY: { in isScalarPred()
376 NewOpc = TargetOpcode::COPY; in convertToPredForm()
417 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), NewOutR) in convertToPredForm()
452 if (MI.getOpcode() != TargetOpcode::COPY) in eliminatePredCopies()
DHexagonSplitDouble.cpp150 case TargetOpcode::PHI: in isFixedInstr()
151 case TargetOpcode::COPY: in isFixedInstr()
304 case TargetOpcode::PHI: in profit()
309 case TargetOpcode::COPY: in profit()
701 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.second) in splitCombine()
710 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.first) in splitCombine()
730 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.first) in splitExt()
770 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), LoR) in splitShift()
772 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), HiR) in splitShift()
829 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), (Left ? HiR : LoR)) in splitShift()
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/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp177 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), in EmitCopyFromReg()
212 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && in CreateVirtualRegisters()
287 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { in getVR()
298 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); in getVR()
341 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); in AddRegisterOperand()
463 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg) in ConstrainForSubReg()
489 if (Opc == TargetOpcode::EXTRACT_SUBREG) { in EmitSubregNode()
511 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg); in EmitSubregNode()
527 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx); in EmitSubregNode()
529 } else if (Opc == TargetOpcode::INSERT_SUBREG || in EmitSubregNode()
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DResourcePriorityQueue.cpp263 case TargetOpcode::EXTRACT_SUBREG: in isResourceAvailable()
264 case TargetOpcode::INSERT_SUBREG: in isResourceAvailable()
265 case TargetOpcode::SUBREG_TO_REG: in isResourceAvailable()
266 case TargetOpcode::REG_SEQUENCE: in isResourceAvailable()
267 case TargetOpcode::IMPLICIT_DEF: in isResourceAvailable()
303 case TargetOpcode::EXTRACT_SUBREG: in reserveResources()
304 case TargetOpcode::INSERT_SUBREG: in reserveResources()
305 case TargetOpcode::SUBREG_TO_REG: in reserveResources()
306 case TargetOpcode::REG_SEQUENCE: in reserveResources()
307 case TargetOpcode::IMPLICIT_DEF: in reserveResources()
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/external/swiftshader/third_party/LLVM/lib/CodeGen/
DExpandPostRAPseudos.cpp128 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
163 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
221 case TargetOpcode::SUBREG_TO_REG: in runOnMachineFunction()
224 case TargetOpcode::COPY: in runOnMachineFunction()
227 case TargetOpcode::DBG_VALUE: in runOnMachineFunction()
229 case TargetOpcode::INSERT_SUBREG: in runOnMachineFunction()
230 case TargetOpcode::EXTRACT_SUBREG: in runOnMachineFunction()
DScheduleDAGEmit.cpp54 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg) in EmitPhysRegCopy()
63 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), VRBase) in EmitPhysRegCopy()
DMachineSSAUpdater.cpp149 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF, in GetValueInMiddleOfBlock()
186 MachineInstr *InsertedPHI = InsertNewDef(TargetOpcode::PHI, BB, in GetValueInMiddleOfBlock()
303 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF, in GetUndefVal()
315 MachineInstr *PHI = InsertNewDef(TargetOpcode::PHI, BB, Loc, in CreateEmptyPHI()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp157 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), in EmitCopyFromReg()
191 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && in CreateVirtualRegisters()
249 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { in getVR()
259 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); in getVR()
302 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); in AddRegisterOperand()
419 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg) in ConstrainForSubReg()
447 if (Opc == TargetOpcode::EXTRACT_SUBREG) { in EmitSubregNode()
467 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg); in EmitSubregNode()
482 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx); in EmitSubregNode()
484 } else if (Opc == TargetOpcode::INSERT_SUBREG || in EmitSubregNode()
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DFastISel.cpp74 while (I != E && I->getOpcode() == TargetOpcode::EH_LABEL) { in startNewBlock()
209 TII.get(TargetOpcode::IMPLICIT_DEF), Reg); in materializeRegForValue()
296 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL) in recomputeInsertPt()
509 TII.get(TargetOpcode::INLINEASM)) in SelectCall()
544 TII.get(TargetOpcode::DBG_VALUE)) in SelectCall()
552 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); in SelectCall()
594 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), in SelectCall()
618 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), in SelectCall()
734 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), in SelectBitCast()
1123 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), in FastEmitInst_r()
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/external/llvm/include/llvm/Target/
DTargetOpcodes.h21 namespace TargetOpcode {
32 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_START && in isPreISelGenericOpcode()
33 Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; in isPreISelGenericOpcode()
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp303 case TargetOpcode::CFI_INSTRUCTION: in GetInstSizeInBytes()
304 case TargetOpcode::EH_LABEL: in GetInstSizeInBytes()
305 case TargetOpcode::IMPLICIT_DEF: in GetInstSizeInBytes()
306 case TargetOpcode::KILL: in GetInstSizeInBytes()
307 case TargetOpcode::DBG_VALUE: in GetInstSizeInBytes()
309 case TargetOpcode::INLINEASM: { in GetInstSizeInBytes()
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/
DMSP430InstrInfo.cpp306 case TargetOpcode::PROLOG_LABEL: in GetInstSizeInBytes()
307 case TargetOpcode::EH_LABEL: in GetInstSizeInBytes()
308 case TargetOpcode::IMPLICIT_DEF: in GetInstSizeInBytes()
309 case TargetOpcode::KILL: in GetInstSizeInBytes()
310 case TargetOpcode::DBG_VALUE: in GetInstSizeInBytes()
312 case TargetOpcode::INLINEASM: { in GetInstSizeInBytes()
/external/llvm/lib/Target/Mips/
DMipsSEFrameLowering.cpp136 case TargetOpcode::COPY: in expandInstr()
159 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst) in expandLoadCCond()
173 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR) in expandStoreCCond()
194 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY); in expandLoadACC()
253 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo) in expandCopyACC()
256 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi) in expandCopyACC()
414 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
448 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
453 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
464 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
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/external/llvm/lib/CodeGen/GlobalISel/
DIRTranslator.cpp91 MIRBuilder.buildInstr(TargetOpcode::G_BR, BrTgt.getType(), TgtBB); in translateBr()
106 return translateBinaryOp(TargetOpcode::G_ADD, Inst); in translate()
108 return translateBinaryOp(TargetOpcode::G_OR, Inst); in translate()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCCodeEmitter.cpp120 case TargetOpcode::PROLOG_LABEL: in emitBasicBlock()
121 case TargetOpcode::EH_LABEL: in emitBasicBlock()
124 case TargetOpcode::IMPLICIT_DEF: in emitBasicBlock()
125 case TargetOpcode::KILL: in emitBasicBlock()
/external/llvm/lib/Target/AVR/
DAVRInstrInfo.cpp451 case TargetOpcode::EH_LABEL: in GetInstSizeInBytes()
452 case TargetOpcode::IMPLICIT_DEF: in GetInstSizeInBytes()
453 case TargetOpcode::KILL: in GetInstSizeInBytes()
454 case TargetOpcode::DBG_VALUE: in GetInstSizeInBytes()
456 case TargetOpcode::INLINEASM: { in GetInstSizeInBytes()

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