| /external/strace/xlat/ |
| D | atomic_ops.in | 8 { OR1K_ATOMIC_UMAX, "UMAX" },
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| /external/python/cpython2/Tools/scripts/ |
| D | h2py.py | 107 UMAX = 2*(sys.maxint+1)
114 val -= UMAX
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 325 SMIN, SMAX, UMIN, UMAX, enumerator
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| D | SelectionDAG.h | 1171 case ISD::UMAX:
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| /external/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 960 X86_INTRINSIC_DATA(avx512_mask_pmaxu_b_128, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),
961 X86_INTRINSIC_DATA(avx512_mask_pmaxu_b_256, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),
962 X86_INTRINSIC_DATA(avx512_mask_pmaxu_b_512, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),
963 X86_INTRINSIC_DATA(avx512_mask_pmaxu_d_128, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),
964 X86_INTRINSIC_DATA(avx512_mask_pmaxu_d_256, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),
965 X86_INTRINSIC_DATA(avx512_mask_pmaxu_d_512, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),
966 X86_INTRINSIC_DATA(avx512_mask_pmaxu_q_128, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),
967 X86_INTRINSIC_DATA(avx512_mask_pmaxu_q_256, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),
968 X86_INTRINSIC_DATA(avx512_mask_pmaxu_q_512, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),
969 X86_INTRINSIC_DATA(avx512_mask_pmaxu_w_128, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),
[all …]
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| D | X86ISelLowering.cpp | 756 setOperationAction(ISD::UMAX, MVT::v16i8, Legal); in X86TargetLowering()
890 setOperationAction(ISD::UMAX, MVT::v8i16, Legal); in X86TargetLowering()
891 setOperationAction(ISD::UMAX, MVT::v4i32, Legal); in X86TargetLowering()
1051 setOperationAction(ISD::UMAX, VT, HasInt256 ? Legal : Custom); in X86TargetLowering()
1314 setOperationAction(ISD::UMAX, MVT::v16i32, Legal); in X86TargetLowering()
1315 setOperationAction(ISD::UMAX, MVT::v8i64, Legal); in X86TargetLowering()
1474 setOperationAction(ISD::UMAX, MVT::v64i8, Legal); in X86TargetLowering()
1475 setOperationAction(ISD::UMAX, MVT::v32i16, Legal); in X86TargetLowering()
1559 setOperationAction(ISD::UMAX, VT, Legal); in X86TargetLowering()
15433 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break; in LowerVSETCC()
[all …]
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| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_opcode_tmp.h | 168 OP12(UMAX)
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstrInfo.td | 93 def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp,
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| D | SIISelLowering.cpp | 228 setTargetDAGCombine(ISD::UMAX); in SITargetLowering()
2697 case ISD::UMAX: in minMaxOpcToMin3Max3Opc()
2810 if (Opc == ISD::UMIN && Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) { in performMinMaxCombine()
2872 case ISD::UMAX: in PerformDAGCombine()
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| D | AMDGPUISelLowering.cpp | 337 setOperationAction(ISD::UMAX, MVT::i32, Legal); in AMDGPUTargetLowering()
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| /external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/ |
| D | select.ll | 473 ; UMAX(UMAX(x, y), x) -> UMAX(x, y)
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 210 case ISD::UMAX: return "umax"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 81 case ISD::UMAX: Res = PromoteIntRes_ZExtIntBinOp(N); break; in PromoteIntegerResult()
1379 case ISD::UMAX: in ExpandIntegerResult()
1681 return std::make_pair(ISD::SETGT, ISD::UMAX); in getExpandedMinMaxOps()
1682 case ISD::UMAX: in getExpandedMinMaxOps()
1683 return std::make_pair(ISD::SETUGT, ISD::UMAX); in getExpandedMinMaxOps()
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| D | LegalizeVectorOps.cpp | 334 case ISD::UMAX: in LegalizeOp()
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| D | LegalizeVectorTypes.cpp | 117 case ISD::UMAX: in ScalarizeVectorResult()
695 case ISD::UMAX: in SplitVectorResult()
2098 case ISD::UMAX: in WidenVectorResult()
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| D | SelectionDAG.cpp | 2464 case ISD::UMAX: { in computeKnownBits()
2609 case ISD::UMAX: in ComputeNumSignBits()
3246 case ISD::UMAX: return std::make_pair(C1.uge(C2) ? C1 : C2, true); in FoldValue()
3529 case ISD::UMAX: in getNode()
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| D | LegalizeDAG.cpp | 3132 case ISD::UMAX: { in ExpandNode()
3139 case ISD::UMAX: Pred = ISD::SETUGT; break; in ExpandNode()
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| /external/llvm/test/Transforms/InstCombine/ |
| D | select.ll | 597 ; UMAX(UMAX(x, y), x) -> UMAX(x, y)
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 876 setOperationAction(ISD::UMAX, VT, Expand); in initActions()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 699 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in addTypeForNEON()
2294 return DAG.getNode(ISD::UMAX, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
9020 case ISD::UMAX: in tryMatchAcrossLaneShuffleForReduction()
9097 if (Op != ISD::SMAX && Op != ISD::UMAX && Op != ISD::SMIN && in performAcrossLaneMinMaxReductionCombine()
9130 (Op == ISD::UMAX && CC != ISD::SETUGT && CC != ISD::SETUGE) || in performAcrossLaneMinMaxReductionCombine()
10133 ReplaceReductionResults(N, Results, DAG, ISD::UMAX, AArch64ISD::UMAXV); in ReplaceNodeResults()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 405 def umax : SDNode<"ISD::UMAX" , SDTIntBinOp,
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| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_from_tgsi.cpp | 800 NV50_IR_OPCODE_CASE(UMAX, MAX); in translateOpcode()
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 4178 ### UMAX ### subsection
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| /external/mesa3d/src/mesa/state_tracker/ |
| D | st_glsl_to_tgsi.cpp | 959 case4d(MAX, IMAX, UMAX, DMAX); in get_opcode()
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| /external/mesa3d/src/gallium/docs/source/ |
| D | tgsi.rst | 1303 .. opcode:: UMAX - Maximum of Unsigned Integers
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