| /external/llvm/test/CodeGen/Mips/cconv/ |
| D | arguments-varargs.ll | 46 ; O32-DAG: addiu [[VA:\$[0-9]+]], [[SP]], 12
47 ; O32-DAG: sw [[VA]], 0([[SP]])
49 ; N32-DAG: addiu [[VA:\$[0-9]+]], [[SP]], 8
50 ; N32-DAG: sw [[VA]], 0([[SP]])
52 ; N64-DAG: daddiu [[VA:\$[0-9]+]], [[SP]], 8
53 ; N64-DAG: sd [[VA]], 0([[SP]])
55 ; Store [[VA]]
56 ; O32-DAG: sw [[VA]], 0([[SP]])
60 ; Increment [[VA]]
61 ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinISelLowering.cpp | 182 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments() local
184 if (VA.isRegLoc()) { in LowerFormalArguments()
185 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
186 TargetRegisterClass *RC = VA.getLocReg() == BF::P0 ? in LowerFormalArguments()
188 assert(RC->contains(VA.getLocReg()) && "Unexpected regclass in CCState"); in LowerFormalArguments()
192 MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg); in LowerFormalArguments()
198 if (VA.getLocInfo() == CCValAssign::SExt) in LowerFormalArguments()
200 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
201 else if (VA.getLocInfo() == CCValAssign::ZExt) in LowerFormalArguments()
203 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 306 CCValAssign &VA = ArgLocs[i]; in LowerCCCArguments() local
307 EVT LocVT = VA.getLocVT(); in LowerCCCArguments()
308 if (VA.isRegLoc()) { in LowerCCCArguments()
331 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
335 assert(VA.isMemLoc()); in LowerCCCArguments()
340 VA.getLocMemOffset(), true); in LowerCCCArguments()
353 if (VA.getLocInfo() == CCValAssign::SExt) in LowerCCCArguments()
355 DAG.getValueType(VA.getValVT())); in LowerCCCArguments()
356 else if (VA.getLocInfo() == CCValAssign::ZExt) in LowerCCCArguments()
358 DAG.getValueType(VA.getValVT())); in LowerCCCArguments()
[all …]
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 232 CCValAssign &VA = RVLocs[i]; in LowerReturn_32() local
233 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_32()
237 if (VA.needsCustom()) { in LowerReturn_32()
238 assert(VA.getLocVT() == MVT::v2i32); in LowerReturn_32()
249 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Flag); in LowerReturn_32()
251 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
252 VA = RVLocs[++i]; // skip ahead to next loc in LowerReturn_32()
253 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1, in LowerReturn_32()
256 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag); in LowerReturn_32()
260 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
[all …]
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 171 for (auto &VA : ArgLocs) { in LowerFormalArguments() local
172 if (VA.isRegLoc()) { in LowerFormalArguments()
174 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
183 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
189 if (VA.getLocInfo() == CCValAssign::SExt) in LowerFormalArguments()
191 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
192 else if (VA.getLocInfo() == CCValAssign::ZExt) in LowerFormalArguments()
194 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
196 if (VA.getLocInfo() != CCValAssign::Full) in LowerFormalArguments()
197 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); in LowerFormalArguments()
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 111 CCValAssign &VA = RVLocs[i]; in LowerReturn() local
112 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
114 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
170 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments() local
183 if (VA.isRegLoc()) { in LowerFormalArguments()
184 if (VA.needsCustom()) { in LowerFormalArguments()
185 assert(VA.getLocVT() == MVT::f64); in LowerFormalArguments()
187 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); in LowerFormalArguments()
213 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
215 if (VA.getLocVT() == MVT::f32) in LowerFormalArguments()
[all …]
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64CallLowering.cpp | 80 CCValAssign &VA = ArgLocs[i]; in lowerFormalArguments() local
82 assert(VA.isRegLoc() && "Not yet implemented"); in lowerFormalArguments()
84 MIRBuilder.getMBB().addLiveIn(VA.getLocReg()); in lowerFormalArguments()
85 MIRBuilder.buildInstr(TargetOpcode::COPY, VRegs[i], VA.getLocReg()); in lowerFormalArguments()
87 switch (VA.getLocInfo()) { in lowerFormalArguments()
|
| /external/llvm/test/tools/llvm-pdbdump/ |
| D | load-address.test | 4 ; RUN: %p/Inputs/LoadAddressTest.pdb | FileCheck --check-prefix=VA %s
9 ; VA: ---EXTERNALS---
10 ; VA: [0x40001010] _main
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | madak.ll | 10 ; GCN: buffer_load_dword [[VA:v[0-9]+]]
12 ; GCN: v_madak_f32_e32 {{v[0-9]+}}, [[VA]], [[VB]], 0x41200000
33 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr…
37 ; GCN-DAG: v_mad_f32 {{v[0-9]+}}, [[VB]], [[VA]], [[VK]]
38 ; GCN-DAG: v_mac_f32_e32 [[VK]], [[VC]], [[VA]]
65 ; GCN: buffer_load_dword [[VA:v[0-9]+]]
66 ; GCN: v_madak_f32_e32 {{v[0-9]+}}, 4.0, [[VA]], 0x41200000
84 ; GCN: buffer_load_dword [[VA:v[0-9]+]]
86 ; GCN: v_mad_f32 {{v[0-9]+}}, [[VA]], [[VB]], 4.0
106 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]]
[all …]
|
| D | madmk.ll | 12 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr…
14 ; GCN: v_mac_f32_e32 [[VB]], 0x41200000, [[VA]]
31 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr…
35 ; GCN-DAG: v_mac_f32_e32 [[VB]], [[VK]], [[VA]]
36 ; GCN-DAG: v_mac_f32_e32 [[VC]], [[VK]], [[VA]]
64 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr…
66 ; GCN: v_mac_f32_e32 [[VB]], 4.0, [[VA]]
129 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr…
150 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr…
|
| /external/clang/test/Parser/ |
| D | cxx-using-declaration.cpp | 4 int VA; variable
9 using A::VA;
15 VA = 1; in main()
|
| /external/clang/test/CXX/special/class.dtor/ |
| D | p3-0x.cpp | 140 struct VA { struct
142 virtual ~VA() {} in ~VA() argument
145 struct VB : VA
149 struct TVB : VA
|
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 323 CCValAssign &VA = ArgLocs[i]; in LowerCCCArguments() local
324 if (VA.isRegLoc()) { in LowerCCCArguments()
326 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
339 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
345 if (VA.getLocInfo() == CCValAssign::SExt) in LowerCCCArguments()
347 DAG.getValueType(VA.getValVT())); in LowerCCCArguments()
348 else if (VA.getLocInfo() == CCValAssign::ZExt) in LowerCCCArguments()
350 DAG.getValueType(VA.getValVT())); in LowerCCCArguments()
352 if (VA.getLocInfo() != CCValAssign::Full) in LowerCCCArguments()
353 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); in LowerCCCArguments()
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeISelLowering.cpp | 720 CCValAssign &VA = ArgLocs[i]; in LowerCall() local
721 MVT RegVT = VA.getLocVT(); in LowerCall()
725 switch (VA.getLocInfo()) { in LowerCall()
741 if (VA.isRegLoc()) { in LowerCall()
742 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
745 assert(VA.isMemLoc()); in LowerCall()
753 unsigned ArgSize = VA.getValVT().getSizeInBits()/8; in LowerCall()
754 unsigned StackLoc = VA.getLocMemOffset() + 4; in LowerCall()
892 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments() local
895 if (VA.isRegLoc()) { in LowerFormalArguments()
[all …]
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 433 CCValAssign &VA = ArgLocs[i]; in LowerCCCArguments() local
434 if (VA.isRegLoc()) { in LowerCCCArguments()
436 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
448 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
454 if (VA.getLocInfo() == CCValAssign::SExt) in LowerCCCArguments()
456 DAG.getValueType(VA.getValVT())); in LowerCCCArguments()
457 else if (VA.getLocInfo() == CCValAssign::ZExt) in LowerCCCArguments()
459 DAG.getValueType(VA.getValVT())); in LowerCCCArguments()
461 if (VA.getLocInfo() != CCValAssign::Full) in LowerCCCArguments()
462 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); in LowerCCCArguments()
[all …]
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiISelLowering.cpp | 441 CCValAssign &VA = ArgLocs[i]; in LowerCCCArguments() local
442 if (VA.isRegLoc()) { in LowerCCCArguments()
444 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
448 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
454 if (VA.getLocInfo() == CCValAssign::SExt) in LowerCCCArguments()
456 DAG.getValueType(VA.getValVT())); in LowerCCCArguments()
457 else if (VA.getLocInfo() == CCValAssign::ZExt) in LowerCCCArguments()
459 DAG.getValueType(VA.getValVT())); in LowerCCCArguments()
461 if (VA.getLocInfo() != CCValAssign::Full) in LowerCCCArguments()
462 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); in LowerCCCArguments()
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86FastISel.cpp | 739 CCValAssign &VA = ValLocs[0]; in X86SelectRet() local
742 if (VA.getLocInfo() != CCValAssign::Full) in X86SelectRet()
745 if (!VA.isRegLoc()) in X86SelectRet()
750 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) in X86SelectRet()
753 unsigned SrcReg = Reg + VA.getValNo(); in X86SelectRet()
755 EVT DstVT = VA.getValVT(); in X86SelectRet()
779 unsigned DstReg = VA.getLocReg(); in X86SelectRet()
788 MRI.addLiveOut(VA.getLocReg()); in X86SelectRet()
1670 CCValAssign &VA = ArgLocs[i]; in DoSelectCall() local
1671 unsigned Arg = Args[VA.getValNo()]; in DoSelectCall()
[all …]
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1103 CCValAssign &VA = ArgLocs[i]; in processCallArgs() local
1104 const Value *ArgVal = CLI.OutVals[VA.getValNo()]; in processCallArgs()
1105 MVT ArgVT = OutVTs[VA.getValNo()]; in processCallArgs()
1110 VA.convertToReg(Mips::F12); in processCallArgs()
1112 VA.convertToReg(Mips::D6); in processCallArgs()
1117 VA.convertToReg(Mips::F14); in processCallArgs()
1119 VA.convertToReg(Mips::D7); in processCallArgs()
1125 VA.isMemLoc()) { in processCallArgs()
1126 switch (VA.getLocMemOffset()) { in processCallArgs()
1128 VA.convertToReg(Mips::A0); in processCallArgs()
[all …]
|
| D | MipsISelLowering.cpp | 2721 CCValAssign &VA = ArgLocs[i]; in LowerCall() local
2722 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); in LowerCall()
2739 VA); in LowerCall()
2745 switch (VA.getLocInfo()) { in LowerCall()
2749 if (VA.isRegLoc()) { in LowerCall()
2761 unsigned LocRegLo = VA.getLocReg(); in LowerCall()
2794 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); in LowerCall()
2796 ISD::SHL, DL, VA.getLocVT(), Arg, in LowerCall()
2797 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); in LowerCall()
2802 if (VA.isRegLoc()) { in LowerCall()
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1581 CCValAssign &VA = ArgLocs[i]; in ProcessCallArgs() local
1582 unsigned Arg = ArgRegs[VA.getValNo()]; in ProcessCallArgs()
1583 MVT ArgVT = ArgVTs[VA.getValNo()]; in ProcessCallArgs()
1590 switch (VA.getLocInfo()) { in ProcessCallArgs()
1593 bool Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), in ProcessCallArgs()
1597 ArgVT = VA.getLocVT(); in ProcessCallArgs()
1601 bool Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), in ProcessCallArgs()
1605 ArgVT = VA.getLocVT(); in ProcessCallArgs()
1609 bool Emitted = FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), in ProcessCallArgs()
1612 Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), in ProcessCallArgs()
[all …]
|
| /external/llvm/tools/llvm-pdbdump/ |
| D | CompilandDumper.cpp | 162 uint64_t VA = Symbol.getVirtualAddress(); in dump() local
165 WithColor(Printer, PDB_ColorItem::Address).get() << format_hex(VA, 10); in dump()
170 << "[" << format_hex(VA, 10) << " - " in dump()
171 << format_hex(VA + Symbol.getLength(), 10) << "]"; in dump()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaISelLowering.cpp | 259 CCValAssign &VA = ArgLocs[i]; in LowerCall() local
264 switch (VA.getLocInfo()) { in LowerCall()
268 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
271 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
274 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
280 if (VA.isRegLoc()) { in LowerCall()
281 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
283 assert(VA.isMemLoc()); in LowerCall()
290 DAG.getIntPtrConstant(VA.getLocMemOffset())); in LowerCall()
363 CCValAssign &VA = RVLocs[i]; in LowerCallResult() local
[all …]
|
| /external/clang/test/Preprocessor/ |
| D | macro_paste_bad.c | 32 #define VA __VA_ ## ARGS__ macro
33 int VA; // expected-warning {{__VA_ARGS__ can only appear in the expansion of a C99 variadic macr… variable
|
| /external/mksh/src/ |
| D | shf.c | 799 #define VA(type) va_arg(args, type) in shf_vfprintf() macro
848 tmp = VA(int); in shf_vfprintf()
911 lnum = (long)VA(ssize_t); in shf_vfprintf()
913 lnum = VA(long); in shf_vfprintf()
915 lnum = (long)(short)VA(int); in shf_vfprintf()
917 lnum = (long)VA(int); in shf_vfprintf()
924 lnum = VA(size_t); in shf_vfprintf()
926 lnum = VA(unsigned long); in shf_vfprintf()
928 lnum = (unsigned long)(unsigned short)VA(int); in shf_vfprintf()
930 lnum = (unsigned long)VA(unsigned int); in shf_vfprintf()
[all …]
|
| /external/skia/src/sfnt/ |
| D | SkOTTable_OS_2.h | 31 struct VA : SkOTTableOS2_VA { } vA; struct
45 static_assert(sizeof(SkOTTableOS2::Version::VA) == 68, "sizeof_SkOTTableOS2__VA_not_68");
|